Xilinx, Inc.

Advanced Micro Devices Corporation

Malema Engineering Corporation

Ge Capital Spacenet Services, Inc.

Other

Philip M Freidin

Charles R Erickson

Stephen M Trimberger

John E Mahoney

Norman Franklin Krasner

Suresh M Menon

Atul V Ghia

Hare Krishna Verma

Warren E Cory

Paul T Sasaki

Edmond Y Cheung

Tsung-Lu Syu

Bernard J New

Rod G Fleck

William M Johnson

Vasisht Mantra Vadi

Cheng-Gang Kong

Adebabay M Bekele

Philip D Costello

Kerry M Pierce

Gigy Baror

Steven B Sidman

William A Wilkie

Michael J Serrone

David George Decker

Ole H Moller

Timothy A Olson

Santiago G Asuncion

Brian W Case

Smeeta Gupta

David I Sorensen

Charles R Erikson

A dispense verification meter for measuring and verifying dispense operations (e.g., actual dispensed volumes) of media dispense systems. The dispense verification meter preferably automatically corrects zero offset drift, preferably samples the flow rate of media being dispensed at a sufficiently high sample rate, and verifies whether the desired dispense operation has been achieved.

Dispense verification meters

One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

High speed configurable transceiver architecture

Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

Network physical layer with embedded multi-standard CRC generator

A programmable digital correlator device, and associated correlation method, with a very efficient structure. In one aspect, two or more correlators share a common data sequence shift register. In another aspect, the data sequence shift register is comprised of random access memory (RAM) modules which allow efficient construction in field programmable gate array (FPGA) logic devices. Two's-complement data samples are multiplied by a reference sequence to produce unfinished two's-complement products, the products are summed with unsigned arithmetic in an adder containing population counters, and a correction factor is added after all other calculations are complete to convert the unsigned result back to a two's-complement number.

Correlator method and apparatus

An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each data frame is divided into discrete serial portions having Y bits each (e.g., a data frame comprises N/Y portions). In parallel mode, the portions are loaded into a segmented configuration register, one portion per programming cycle, such that Y bits are loaded into the segmented configuration register in parallel. On each programming clock cycle during parallel loading, all the bits of a data frame portion are simultaneously loaded into the segments of the configuration register (at the first bit position for each segment) such that each segment receives one bit per programming cycle. The bits of the configuration register are then shifted down by one and the cycle repeats for the next data frame portion. Under this mechanism, Y bits are loaded in parallel into the configuration register for increased transfer rate. The architecture of the novel configuration register is such that it is configurable in a serial mode to receive a single serial bit stream of the N bit data frame for downward compatibility.

Configurable parallel and bit serial load apparatus

A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU. The architecture reuses the IC's complement of logic and other functional elements continuously during a logic cycle to implement the circuit as a series of circuit stages over time using a relatively limited number of logic and other functional elements to implement each stage. The GIMU is coupled to address and data buses and the data bus is coupled to each logic module. The GIMU contains individually addressable memory cells that are shared between logic modules across different time intervals providing an extremely flexible signal path between logic modules. The GIMU has a separate read and write port for each logic module.

Virtual high density programmable integrated circuit having addressable

Logic is represented in a schematic capture program as a generic symbol. The generic symbol represents a single underlying logic circuit, thereby decreasing library space. The generic symbol includes a configuration memory which is represented on the symbol by a plurality of pins. The generic symbol is configured by indicating the logic signals placed on the plurality of pins. In this manner, the generic symbol significantly increases the design choices available to the end user. Moreover, the generic symbol allows access to the underlying logic of the circuit via the selected bit pattern, thereby advantageously permitting the end user to perform functional simulation within the schematic environment. In one embodiment, a plug symbol is provided to schematically connect to the generic symbol. This plug symbol represents a predetermined pattern of bits, thereby significantly simplifying configuring the logic in the schematic capture program.

Method for providing multiple function symbols

A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship. In one form of the invention, an inventer adapted to invert one of the reference input clock and output clock signals, and a divide by N circuit for lowering the clock frequency while roughly adjusting the delay.

Phase-locked delay loop for clock correction

A configurable logic block (CLB) in the dual port mode uses one address to write the same information in a first RAM and a second RAM. The input signals provided to the second function generator can be used to read, independently from and even asynchronously with, the write operation, thereby dramatically increasing the speed of applications using the two sets of RAM. A CLB in the synchronous mode latches the appropriate address and data signals, and generates a strobed write enable signal. The strobed signal is self-timed, i.e. the write operation is fully automatic, thereby ensuring that a write operation occurs within one clock cycle.

Synchronous dual port RAM

The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session. Both serial and parallel data streams may be checked.

Error detection structure and method for serial or parallel data stream

Growing community of inventors

Sunnyvale, CA, United States of America

Philip M Freidin