International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Philip Louis Weinstein

Justin Potok Bandholz

Kevin Michael Reinberg

Clifton Ehrich Kerr

Joseph Eric Maxwell

Christopher Collier West

Zachary Benson Durham

Pravin S Patel

Kevin S D Vernon

Kevin S Vernon

Brian Michael Kerrigan

Edward John McNulty

Peter Robert Seidel

Gary David Cudak

Christopher J Hardee

Adrian Xavier Rodriguez

Luke David Remis

William Joseph Piazza

Jimmy Grant Foster, Sr

Michael DeCesaris

James Joseph Parsonese

Thomas Dixon Pahel, Jr

Srinivas Cheemalapati

Timothy Schlude

Methods and systems for fan speed control based on memory margin are disclosed. According to an aspect, a method includes determining an operating margin of a memory interface. The method also includes determining whether the operating margin of the memory interface meets a predetermined condition. Further, the method includes controlling a speed of a computing system cooling fan based on the operating margin in response to determining the operating margin meets the predetermined condition.

Fan speed and memory regulator control based on memory margin

Mapping computers and ports of power distribution units in a data center, the data center including a plurality of computers and a data center management server, each computer in the data center connected for power to one of a plurality of power distribution unit ('PDU') ports of a PDU, each PDU connected through the communications module and a data communications network to the data center management server, including generating, by a power modulating module of a computer, a power consumption signal in the PDU, the power consumption signal encoding a unique identification of the computer; demodulating, by the PDU, the power consumption signal, including retrieving from the signal the unique identification of the computer; and reporting, by the PDU to the data center management server, an association of the unique identification of the computer and a PDU port.

Mapping computers and ports of power distribution units in a data center

An apparatus for avoiding a damaged region on a touchscreen is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a damage location module that determines a location of an area of damage on a touchscreen of a computing device. The area of damage includes damage to the touchscreen. The apparatus, in one embodiment, includes a display location module that determines a location of one or more display items commanded to be displayed on the touchscreen. Each display item includes a location to be displayed on the touchscreen. The apparatus includes, in one embodiment, a rearrangement module that alters a location of a display item to be displayed in the area of damage where the display item is moved to a location on the touchscreen outside the area of damage on the touchscreen.

System and method for altering interactive element placement based around damaged regions on a touchscreen device

A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

DIMM riser care with an angled DIMM socket and a straddle mount DIMM socket

Methods, apparatus, and products are disclosed for implementing a redundant array of inexpensive drives ('RAID') with an external RAID controller and hard disk drives from separate computers, including configuring by the external RAID controller a RAID array, the RAID array comprising hard disk drives from the separate computers, the external RAID controller comprising a hardware RAID controller installed externally with respect to the separate computers, and storing, by one or more of the separate computers through the external RAID controller, computer data on the RAID array.

Implementing a redundant array of inexpensive drives

Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Optimizing a physical data communications topology between a plurality of computing nodes

According to one embodiment, an apparatus has first and second connectors configured for removably connecting to one another. The first connector circuit has a first differential amplifier, a first differential signal path, a first capacitor section capacitively coupling the first differential amplifier to the first differential signal path, and a first DC biasing circuit for imparting a first DC bias to the first differential signal path opposite the first capacitor section. The second connector circuit has a second differential amplifier, a second differential signal path, a second capacitor section capacitively coupling the second differential amplifier to the second differential signal path, and a second DC biasing circuit for imparting a second DC bias to the second differential signal path opposite the second capacitor section having a different magnitude than the first DC bias when the first and second connector are not connected. One or both of the first and second connector circuits is configured for detecting a change in the first or second DC bias and outputting a connection status signal in response to the detected change.

Self-detecting electronic connection for electronic devices

DIMM riser card with an angled DIMM socket and a straddled mount DIMM socket

Methods and apparatus for workload balancing among power switching components in a multiphase switching power supply, the power supply including one set of power switching components for each switching phase, where workload balancing includes: dropping one or more switching phases when output current demand on the power supply drops below a predetermined threshold, leaving at least one active switching phase; and rotating the at least one active switching phase among all sets of power switching components.

Workload balancing among power switching components in a multiphase switching power supply

Data communications among electronic devices within a computer, including transmitting, from a transmitting device to a first translation device, data communications encoded according to an unreliable wireline data communications protocol; translating, by the first translation device, the data communications from the encoding of the unreliable wireline data communications protocol to an encoding of a reliable wireless data communications protocol; transmitting, by the first translation device to a second translation device, the data communications according to the reliable wireless data communications protocol; translating, by the second translation device, the data communications from the encoding of the reliable wireless data communications protocol to the encoding of the unreliable wireline data communications protocol; and transmitting, by the second translation device to a receiving device, the data communications according to the unreliable wireline data communications protocol.

Data communications among electronic devices within a computer

Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.

Detecting an increase in thermal resistance of a heat sink in a computer system

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units ('CPUs'); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Structure for a memory switching data processing system

A memory switching data processing system including one or more central processing units ('CPUs'); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Memory switching data processing system

Methods, systems and computer program products for packet prioritization based on delivery time expectation. Exemplary embodiments include receiving a packet for routing, estimating a TimeToDestination for the packet, the estimating performed by a Internet Control Message Protocol, reading a TimeToDeliver field from each the Internet Protocol Header of the packet to extract data on when the packet needs to be at the destination, determining a MaxQueueDelay for the packet, the MaxQueueDelay calculated by subtracting the TimeToDeliver from the TimeToDestination, passing a lower priority packet if the lower priority packet has a lower MaxQueueDelay, and decrementing the TimeToDeliver by an amount of time the network router has had the packet in the queue before passing the packet to a next router, thereby communicating to the next router how much time is left before the packet must be delivered.

Growing community of inventors

Apex, NC, United States of America

Philip Louis Weinstein