International Business Machines Corporation

Other

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Macronix International Co., Ltd.

Philip L Flaitz

Chih-Chao Yang

Yun-Yu Wang

Rajarao Jammy

Johnathan E Faltermeier

Lawrence Alfred Clevenger

Timothy Joseph Dalton

Herbert Lei Ho

Thomas M Shaw

David M Dobuzinsky

James J Demarest

Michael Wayne Lane

Darryl D Restaino

Chester T Dziobkowski

Stefanie Ruth Chiras

James R Lloyd

Oleg Gluschenkov

Yun Yu Wang

Jochen C Beintner

Byeong Yeol Kim

Rama Divakaruni

James N Humenik

Srinivasa S Reddy

Derren Neylon Dunn

Mihel Seitz

Hiroshi Takato

Herbert Palm

Raj N Master

Paul H Palmateer

Akira Sudo

Carol J Heenan

Yoichi Takegawa

Seiko Yoshida

John Preston Benedict

James F Moseman

Erwin N Hammerl

Robert W Churchwell

Chung H Lam

Daniel C Edelstein

John Ulrich Knickerbocker

Hsiang-Lan Lung

Takeshi Nogami

Sampath Purushothaman

Subramanian Srikanteswara Iyer

Ming-Hsiu Lee

Ravikumar Ramachandran

Babar Ali Khan

Matthew Joseph Breitwisch

Yen-Hao Shih

Stephen Mark Rossnagel

Chandrasekhar Narayan

Viraj Yashawant Sardesai

Paul Christian Parries

Charles Hampton Perry

Lester W Herron

Sarah Huffsmith Knickerbocker

Simone Raoux

Chieh-Fang Chen

Robert W Nufer

Patrick William Dehaven

Hua Shen

John Acocella

Radhika Srinivasan

Joseph M Harvilchuck

Srinivasa N Reddy

Michael Maldei

Frieder Heinrich Baumann

Jeffery L Hurd

Colleen M Snavely

Michael M Iwatake

Philip Edward Batson

Steven P Young

Francis G Trudeau

Lisa Y Ninomiya

Arlyne M Flanagan

Darren N Dunn

Dinah S Weiss

A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Dielectric mesh isolated phase change structure for phase change memory

A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60 atomic % such that the barrier layer has a resulting amorphous structure.

Copper interconnect structure with amorphous tantalum iridium diffusion barrier

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO&#x2014; or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Pitcher-shaped active area for field effect transistor and method of forming same

In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

Method to enhance epitaxial regrowth in amorphous silicon contacts

In accordance with the present invention, a method for forming a crystalline silicon nitride layer, includes the steps of providing a crystalline silicon substrate with an exposed surface, precleaning the exposed surface by employing a hydrogen prebake and exposing the exposed surface to nitrogen to form a crystalline silicon nitride layer. Also, a trench capacitor, in accordance with the present invention, includes a crystalline silicon substrate including deep trenches having surface substantially free of native oxide. A dielectric stack, including a crystalline silicon nitride layer, is formed on the sidewalls of the trenches. The dielectric stack forms a node dielectric between electrodes of the trench capacitor.

Method for forming crystalline silicon nitride

A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.

Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization

A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.

Dopant control of semiconductor devices

Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Shallow trench isolation with oxide-nitride/oxynitride liner

A method of forming an adherent layer of metallurgy on a ceramic substrate which includes the steps of obtaining a ceramic material containing a polymeric binder and copper metallurgy patterns within the ceramic body. In one embodiment of the invention, the ceramic body also contains MgO. Thereafter, a surface layer of metallurgy is formed on the surface of the ceramic body. In one embodiment, the surface layer is nickel and in another embodiment, the surface layer is copper or gold. Then, the ceramic body undergoes a sintering cycle which includes the steps of pyrolysis, binder burnoff and, lastly, densification and, in some cases, crystallization. During densification and crystallization, there is a predetermined steam atmosphere which meets the following requirements: a partial pressure of oxygen less than that necessary to satisfy the equilibrium equation 4Cu+O.sub.2 =2Cu.sub.2 O; and a partial pressure of oxygen less than or equal to that necessary to satisfy the equilibrium equation 2Ni+O.sub.2 =2NiO for nickel in said surface metallurgy.

Method of forming an adherent layer of metallurgy on a ceramic substrate

A method for co-sintering ceramic/metal multi-layered ceramic substrates wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are substantially eliminated. Binder-burnoff is substantially not aggravated during this process as well. The process is accomplished by applying selective forces to the surfaces of the ceramic substrates to control lateral movement while allowing Z direction shrinkage movement. Frictional force means, pneumatic forced means and weights are among the means used to supply forces. Cerium oxide is used in certain embodiments to enhance binder-burnoff.

Method and means for co-sintering ceramic/metal MLC substrates

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Hopewell Junction, NY, United States of America

Philip L Flaitz