Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Philip L Barnes

Larry Jay Thayer

Barry Joseph Arnold

Kenneth Koch, Ii

David Marshall

A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.

Output buffer slew rate control using clock signal

A method of enhancing noise margin on digital signal lines of a system includes steps of evaluating impedances and lengths of the digital signal lines. Resonances of each digital signal line are determined, and target waveforms for each digital signal line optimized for noise margin are determined. A configuration is generated for a programmable device driver to configure the device driver to generate the waveform optimized for noise margin. An alternative embodiment selects waveforms, and corresponding configurations, from a group of possible waveforms at boot time to ensure that data is transferred with optimum noise margins. Also claimed is apparatus embodying bus drivers capable of driving a bus with a waveform approximating blended trapezoidal and sinusoidal edge shapes, this waveform being optimum for noise margin in certain systems having multidrop busses.

Method and apparatus for high speed bus having adjustable, symmetrical, edge-rate controlled, waveforms

A method and apparatus for mitigating the hysteresis effect in a sensing circuit used in the evaluation of a property of a system under test. A state monitor circuit is included for detecting the sensing circuit's state upon evaluating the system's property, e.g., a data out signal level. A feedback control generator is provided for generating a control signal operable to transition the sensing circuit's state to a balanced state, wherein the control signal's logic state is capable of being modified substantially immediately upon completion of the evaluation operation.

Method and apparatus for mitigating the hysteresis effect in a sensing circuit

A method and apparatus for mitigating the history effect in silicon-on-insulator (SOI)-based circuitry, e.g., data interface circuitry operable as a single-ended off-chip signal receiver in a VLSI component such as a microprocessor. A sense amplifier (sense amp) latch circuit arrangement includes a sense amp operable to sense data and a latch operable to hold the sensed data. When data is available, the sense amp generates a pair of complementary data signals responsive to a control signal used for alternating the sense amp's operation between an evaluation phase and an equilibration (i.e., pre-charge) phase. A feedback circuit portion is operable to modify the control signal's logic state within a clock phase associated with one of the two complementary clocks provided to the interface circuitry. Since the equilibration phase is entered combinationally off the evaluation phase, both evaluation and equilibration can be triggered from the same clock edge.

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Plano, TX, United States of America

Philip L Barnes