Ami Semiconductor, Inc.

Philip John Cacharelis

Greg Scott

Thierry Coffi Hervé Yao

Pierre André Claude Gassot

An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.

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Oudenaarde, Belgium

Philip John Cacharelis