National Semiconductor Corporation

National Semiconductor Company

Philip J Cacharelis

Richard B Merrill

Douglas Robert Farrenkopf

Kevin E Brehmer

Kamesh V Gadepally

Michael J Hart

Jeffrey Robert Perry

Martin Harold Manley

Narasimha Narahari

A liquid crystal on silicon (LCOS) display pixel with dual storage capacitors for increasing the storage capacitance of the charge storage node for the liquid crystal pixel. The two capacitors are in a stacked arrangement. The bottom capacitor is formed by using a buried diffusion layer as the bottom electrode, a first layer of polysilicon (poly) as the top electrode and silicon dioxide as the dielectric. The top capacitor is a poly-to-poly capacitor formed by using the first layer of poly as the bottom electrode and a second layer of poly as the top electrode.

Liquid crystal on silicon (LCOS) display pixel with multiple storage capacitors

A pixel cell array for a reflective silicon light valve features a planar surface alignment layer of uniform thickness over the active pixel electrodes. The surface alignment layer is formed by flowing and curing multiple quantities of alignment material. A first quantity of low viscosity alignment material is spun over the surface and settles into trenches between the raised active pixel electrodes. Curing of the first quantity of alignment material forms a lower alignment layer in the trenches, reducing topography offered by the array surface. A second, larger quantity of higher viscosity alignment material is then spun over active pixel electrodes and the lower alignment layer. The second quantity of alignment material is then cured to form a surface alignment layer. Because of reduction in topography of the array surface by the lower alignment layer, the surface alignment layer is both substantially planar and of uniform thickness across the surface of the active pixel electrode. Each of these properties improve the resolution of the pixel cell by reducing misalignment of the LC attributable to topography offered by the surface alignment layer.

Process for forming silicon LC pixel cell having planar alignment layers of uniform thickness

A process flow for forming a pixel cell for a light valve implements the furnace alloy/sintering step prior to deposition of the reflective metal layer from which the active pixel electrodes are to be formed. In this manner, the active pixel electrodes are spared loss of reflectance associated with prolonged exposure to high temperatures of the furnace alloy/sintering step. Adequate suppression of surface state charges created after the furnace alloy/sintering is ensured by performing a rapid thermal anneal at the conclusion of the process flow.

Liquid crystal display fabrication process using a final rapid thermal anneal

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Fabrication of semiconductor structure having two levels of buried

An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor; and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.

Memory transistor having underlapped floating gate

Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricatable from a semiconductor structure having two levels of buried regions. In a typical embodiment lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. Upper buried regions of opposite conductivity type are similarly situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is normally configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate. Complementary bipolar transistors can be integrated with complementary field-effect transistors in the structure.

Semiconductor structure having two levels of buried regions

Method of fabricating integrated circuit chip containing EEPROM and

An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM cell; a second mask layer is used to define a tunneling region of the memory transistor;and a third mask layer is used to define a floating gate of the memory transistor and a gate of the select transistor. A control gate of the memory transistor is formed using the same mask that is used to define the gates of the CMOS transistors. The third and fourth mask layers may also be used to form the lower and upper electrodes, respectively, of a capacitor.

Method of fabrication of integrated circuit chip containing EEPROM and

A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.

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Menlo Park, CA, United States of America

Philip J Cacharelis