Bell Telephone Laboratories

Multilink Inc.

American Telephone & Telegraph Co., At&t Bell Laboratories

Avaya Holdings Limited

Spectel Operations, Limited

Philip J Baun, Jr

Bruce S Allen

Marshall B Garrison

Paul P Martel

Arthur P Leondires

Joseph Elide Landry

Bruce Walsh

Stephen K Eng

Joseph F Carriere

Robert S Horne

Jonghee Lee

Philip S Brodsky

Nonthiya Watson

David C Rhodes

Robert W Horne

Bruce E Walsh

John T Watson

Gary R McCarthy

Richard LeBlanc

Thomas B Merrick

Thomas M Nolan

According to the principles of the invention, there is provided a conferencing system that dynamically assigns calls to DSP resources. The system may attempt to process each audio conference on a single DSP node, so that information about conference participants does not need to be shared across DSP nodes. Further, the mapping of call channels to resources within a DSP node may be automated so that it is transparent to a conferencing system control application. Where more than one DSP node is required for a particular conference, there is further provided a system for linking DSP nodes. There are also provided methods for managing audio conferencing resources.

Audio conferencing system

A processor unit for a multipoint audio-video conferencing system, wherein the processor unit includes a host processor for controlling operation of the audio-video conferencing system. Controlling operation includes controlling the performance of a plurality of functions associated with servicing each of a plurality of communications connections, each of the connections being between a conferee terminal and the audio-video conferencing system. The processor unit also includes a plurality of digital signal processors, in communication with each other over a first bus and in communication with and controlled by the host processor over a second bus. Each digital signal processor includes an associated configuration element for adaptively configuring a selected digital signal processor to perform processing required by a selected one of the functions associated with servicing a selected one of the communications connections. The processing required by the conferencing functions is distributed between the plurality of digital signal processors.

Audio-video conferencing system

An improved system for connecting and processing a plurality of phone user in a teleconference on a common digital bus. The apparatus includes a plurality of digital processing units (DSPs) associated with selective phone lines and in communication with each other. Each DSP determines an activity status for each associated phone line and transmits that status to the other DSPs, The DSPs create and update respective identical 'talk-lists' which reflect the active conferees whose voice data is currently being output on the phone channels. The system thus provides scaleable teleconferencing in a real-time configuration without switching between the various signals on the common bus such that each incoming caller or even a plurality of conferences has equal priority.

Method and apparatus for audio teleconferencing a plurality of phone

A channel bank unit for interfacing baseband user signals with a PCM carrier communications channel. The channel bank unit includes a circuit allowing verification of the transmission interity between the channel bank unit and external equipment having two-way communication with the channel bank unit. The circuit includes a first portion for evaluating the reception integrity of signals received from the external equipment and a second portion for imposing a parity sense on the signals transmitted to the external equipment that is related to the evaluation results of the first portion.

D-5 Channel bank control structure and controller

A digital channel bank (11) has a plurality of channel units (17) interconnected to a digroup controller (10) over a shared data bus (30). A data processing circuit (FIG. 2) is included in each channel unit for the purpose of reducing the received signaling status information transmitted from each channel unit to the controller. The circuit (e.g., gates 24-27) serves to prevent single bit errors from being recognized as changes in the received signaling state. The circuit (gate 28) also insures that only changes in the signaling status, rather than current status, are reported to the controller. The circuit also incorporates a predetermined amount of delay for the purpose of eliminating multiple messages to the controller when the A and B path signaling bits change in adjacent signaling frames.

Processing apparatus for data rate reduction

A parity circuit (FIG. 6) for n signals comprises n-1 parity building blocks (61-67) connected in a parity tree configuration. Each parity building block comprises three interconnected NAND gates (41-43). A first pair of signal inputs (A and B) are connected to the input of the first and second NAND gates (41 and 42), and a second pair of signal inputs (C and D) are connected to the input of the first and third NAND gates (41 and 43). The output of the first NAND gate (41) is coupled to the input of the second and third NAND gates (42 and 43). The pairs of inputs are controlled so that at least one signal in each pair is high ('1').

Parity circuits

Growing community of inventors

Andover, MA, United States of America

Philip J Baun, Jr