Synopsys, Inc.

Philip Hui-Yuh Tai

Yi-Min Jiang

Sung-Hoon Kwon

Hsien-Shih Chiu

Kai-Shun Hu

Henry Sheng

Shao-Yun Fang

Sheng-Wei Yang

Guo-Ting Wang

Cindy Chin-Fang Shen

Tao-Chun Yu

Chin-Hsiung Hsu

An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).

Pin accessibility prediction engine

In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph, and. comparing the block graph with each of the one or more pattern graphs to determine whether the at least one violating position is cleared. In circumstances where a match is found between the block graph and the each of the one or more pattern graphs, the computer-implemented method further comprises changing the one or more design patterns and repeating the step of comparing until there is no further match found.

User-defined rule engine

A design of an integrated circuit device, in which locations of power wires and memory/logic circuitry are known, is analyzed by at least: identifying intersections of power wires with one another, for power wires that are electrically connected to one another through vias; segmenting power wires, at their intersections; preparing estimates of conductance of vias and wire segments in the form of conductance matrix G; and preparing estimates of current I at each intersection based on power consumed by surrounding circuitry, and current vector 'I' and conductance matrix 'G' are used to solve for voltage drop &#x394;V, in a matrix equation G&#x394;V=I, and the voltage drop is displayed, to allow a human to make changes in the design. Pins of unconnected hard macros are temporarily connected to their closest wires, and current therethrough is included in the estimates.

Power network analyzer for an integrated circuit design

A power pad synthesizer automatically proposes locations of pads that are to carry power in an integrated circuit design. Specifically, a computer is programmed to prepare the plan in at least two stages as follows. In a first stage, a number of pads are proposed around a periphery of the IC design such that an attribute (e.g. maximum voltage drop) satisfies a predetermined condition (e.g. below a user-specified limit that's scaled up by a predetermined amount). In a second stage, the computer automatically identifies a specific location in the design for having an attribute value that satisfies another predetermined condition (e.g. interior location of maximum voltage drop or peripheral location of maximum current), and automatically proposes one or more additional pads at one or more peripheral locations that are identified by a predetermined rule based on the identified specific location (e.g. having the same x-coordinate or the same y-coordinate).

Power pad synthesizer for an integrated circuit design

Growing community of inventors

Cupertino, CA, United States of America

Philip Hui-Yuh Tai