International Business Machines Corporation

Philip George Shephard, Iii

Vikas Agarwal

Michael Ju Hyeok Lee

William Vincent Huott

Robert Walter Berry, Jr

Gulsun Yasar

Manoj N Kumar

Yuen H Chan

Kevin Franklin Reick

Jose Angel Paredes

Timothy Michael Skergan

Sam Gat-Shang Chu

Christopher John Engel

Vasant B Rao

Pradip Patel

Norman Karl James

Jeffrey Paul Soreff

Saiful Islam

Terry Lee Leasure

Brian Chan Monwai

Bernd K Koenemann

Ravichander Ledalla

William J Scarpero, Jr

Kenneth D Wagner

Andrew James Bianchi

Neil R Vanderschaaf

T W Griffith

Frederick J Cox

Tai Dinh Ngo

Edelmar Seewann

Paul R Turgeon

Joseph B Hanley, Iii

Marco Zamora

Chi Duy Bui

A method for hierarchical analysis of electronic circuits comprises selecting a first one of a plurality of abstraction levels of a general design model (GDM). The GDM comprises a first design description of electronic circuits at a plurality of abstraction levels and a plurality of foci, organized into sub-blocks. The method selects a first focus of the plurality of foci to select a first sub-block. The method identifies incomplete electronic circuits in the selected first sub-block. The method generates a second design description of the first sub-block to exclude identified incomplete electronic circuits, wherein the second design description is suitable for electronic design analysis (EDA). The method stores the generated second design description for subsequent use. Subsequent iterations thereby include all components of circuits that were incomplete in prior iterations.

System and method for improved hierarchical analysis of electronic circuits

A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge 'outlier' cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.

System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model

A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.

Shift register latch with embedded dynamic random access memory scan only cell

A method for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge 'outlier' cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.

Method for verifying performance of an array by simulating operation of edge cells in a full array model

An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

Multifunctional latch circuit for use with both SRAM array and self test device

A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.

Test method for guaranteeing full stuck-at-fault coverage of a memory array

Repairing arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the arrays is selected for testing. Data patterns are sent from the test engine to the subset of arrays at a plurality of operating parameters. A response is received at the test engine from the subset of arrays at the operating parameters. The received response is compared to an expected response using the test engine, wherein the processor controller determines if additional test failures were detected by the test engine for the subset of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.

JTAG-based software to perform cumulative array repair

Each match word line driver circuit associated with a content addressable memory (CAM) utilizes a scannable latch for testing. The scannable latches associated with a particular CAM are connected together, scan output of one to scan input of the next, forming a scanning latch chain. In test mode the scannable dynamic latch is used either for testing CAM match circuits or for driving word lines to test the RAM array. Testing CAM match circuits is accomplished by patterning the CAM array with known storage values. The match circuitry then compares an effective address to each storage value and the results are scanned out. Testing the RAM array is performed by driving each word line with a known scan value. Each word line responds the scan value and a sense amplifier outputs a RAM array value based on the word line.

System and method of generating dynamic word line from the content addressable memory (CAM) &ldquo;hit/miss&rdquo; signal which is scannable for testability

A method and apparatus for testing a plurality arrays on a processor with an on chip built in self test engine on the processor. A subset of the plurality arrays on the processor is selected for testing using a control mechanism to selectively enable testing of the subset. Data patterns from the on chip built in self test engine are sent to the plurality arrays on the processor. A response is received at the on chip built in self test engine from the plurality arrays. The response from the plurality arrays is compared to an expected response using the on chip built in self test engine.

Method and apparatus for selectively enabling and disabling functions on a per array basis

The present invention adds a programmable expect generator (PEG) that generates expected patterns of output for comparison to the actual outputs of an array while undergoing a complex test input sequence. The output of a programmable array built-in self test (PABIST) controller has its output increased to include separate control bits and a mask bit for a PEG. The PEG in one embodiment of the invention is substantially similar to a data control register that is programmed by a sequence of commands to generate the array input data patterns for testing an array. The program sequence that controls the PABIST and generates the input address, data and read/write patterns also outputs separate control bits to direct the PEG to generate expected outputs from the array when data from corresponding read addresses are read. The incorporation of a mask bit that accompanies each group of PEG control bits is used to inhibit the compare function that compares the output of the array to the output of the PEG. The mask bit controls when outputs of the array under test are compared to the PEG.

Programmable array built-in self test method and controller with programmable expect generator

The present invention discloses a method and system for testing imbedded logic arrays. An imbedded logic array is first tested for read/write functionality and then a test sequence is run to test the imbedded logic function. The method of the present invention writes a first data pattern to all addresses in an imbedded logic array. Next a second data pattern is written to a specific address followed by a read selecting all addresses concurrently. The output of the imbedded logic array, during this test, is the logic combination of the first data pattern and the second data pattern at the address where the second data pattern was written. By comparing the imbedded logic array output to an expected output the imbedded logic of the array is tested. The present invention anticipates imbedded logic arrays where the expected data output is not a previously written pattern. A programmable expect generator (PEG) is added that generates expected patterns of output for comparison to the actual outputs of an imbedded logic array. In this embodiment of the present invention the same programmable Array Built-In Self Test (PABIST) system used to test the read/write functionality may be used to facilitate testing of the imbedded logic function of an imbedded logic array.

Programmable array built-in self test method and system for arrays with imbedded logic

A method and apparatus for testing a contents-addressable-memory type structure using a simultaneous write-thru mode in an array is provided. The circuit to be tested has combinational logic and an array, and the array has bit cells and a logic cells. Each logic cell is uniquely associated with a bit cell such that an output of a bit cell provides an input to a logic cell, and each set of logic cells for an address of the array provides an output data vector from the array. Each cone of logic in the combinational logic receives an output data vector from an associated address in the array as an input data vector, and each cone of logic in the combinational logic is independent from other cones of logic in the combinational logic. A test vector is input to a write port of the array, and a set of logic cell input values are also input into the array. A test write-thru mode signal simultaneously asserts all write wordline signals of the array associated with the write port in order to write the test vector to all addresses of the array. Test vectors can then be applied simultaneously to all the cones in the combinatorial logic instead of having to apply them to one array address at a time, thereby making it feasible to test this combinatorial logic using standard logic testing techniques. The non-CAM compare type array operations are then tested using ABIST techniques.

Method and apparatus for testing a contents-addressable-memory-type structure using a simultaneous write-thru mode

An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy.

Programmable built-in self test method and controller for arrays

A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.

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Round Rock, TX, United States of America

Philip George Shephard, Iii