Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global Unlimited Company

Analog Devices Global

Philip Eugene Quinlan

Kenneth J Mulvaney

Patrick G Crowley

Kenneth T Deevy

Mark Alan Lemkin

Lance Robert Doherty

Bram Nauta

William Hunt

Muhammad Kalimuddin Khan

Eric Antonius Maria Klumperink

Miguel Chanca

Bartholomeus Jacobus Thijssen

Juan Miguel Judit Ugsimar

Vernon H Valles

Erwin Paul Ramos Santiago

Catherine Francisco Andaya

Joana Rochelle Ortiz Maramba

Thor Juneau

Hyman Shanan

Janos Kovacs

Niall Kevin Kearney

Dermot G O'Keeffe

Shane O'Mahony

Ronald Kroesen

Peter Real

Cornelius O'Mahony

Gary Wayne Ng

Patrick Griffin

Mairtin Walsh

Justine Mary McCormack

Khaled Hassan

Vincent Foley

Ronan Casey

Muhammad Khan

Techniques to improve the immunity of wireless battery systems by transmitting heavily-coded signals, e.g., using multiple chips of a sequence for each bit of information, to trade data rate for interference or jamming immunity as a response once a noisy environment is identified. The techniques provide the system with a noise immunity operating mode (or high-immunity transmit and receive mode) that can improve resilience to interference or jamming by reducing the data rate. One option for reducing the data rate is by slowing down the transmission bit rate to reduce the occupied transmit bandwidth to minimize the probability of collisions with interfering signals. Another option is though digital coding methods using Forward Error Correction such as Convolutional Coding, Reed-Solomon Coding and Turbo coding. A third option is with RF spread spectrum techniques such as Direct Sequence Spread Spectrum (DSSS) or Frequency Hopped Spread Spectrum (FHSS).

High-immunity wireless communication for battery management systems

A radio frequency, RF, receiver circuit that is configured to simultaneously monitor a two or more different RF frequencies. The RF receiver circuit uses a sub-sampler to sub-sample an RF signal that is at any of the monitored RF frequencies, and the sub-sampled signal is then demodulated and a digital code that was encoded in the RF signal is recovered. The RF receiver circuit may be particularly low power, in part owing to using the same sub-sampler for each of the two or more monitored RF frequencies, and not relying on superheterodyning. Furthermore, monitoring two or more different RF frequencies simultaneously means that signals received on the monitored RF frequencies may be acted on very quickly. These characteristics make the RF receiver circuit particularly suitable for use in low-power wake-up receivers, such as Bluetooth Low Energy (BLE) wake-up receivers.

Radio frequency receiver circuit

A radio frequency, RF, receiver circuit is configured to simultaneously monitor a two or more different RF frequencies. The RF receiver circuit uses a sub-sampler to sub-sample an RF signal that is at any of the monitored RF frequencies, and the sub-sampled signal is then demodulated and a digital code that was encoded in the RF signal is recovered. The RF receiver circuit may be particularly low power, in part owing to using the same sub-sampler for each of the two or more monitored RF frequencies, and not relying on superheterodyning. Furthermore, monitoring two or more different RF frequencies simultaneously means that signals received on the monitored RF frequencies may be acted on very quickly. These characteristics make the RF receiver circuit particularly suitable for use in low-power wake-up receivers, such as Bluetooth Low Energy (BLE) wake-up receivers.

A system and method for monitoring components of a vehicle includes a manager and a wireless node. The manager is positioned on the vehicle and configured to wirelessly transmit a wake signal in response to an event. The wireless node positioned to monitor a component of the vehicle and includes an antenna, a wakeup circuit, and a node transceiver. The wakeup circuit is connected to the antenna and configured to monitor for the wake signal, and the node transceiver is configured to perform wireless communication with the manager. The wakeup circuit is configured to power on the node transceiver upon receipt of the wake signal.

Radio-frequency wakeup for vehicle systems

Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.

Systems and methods for analog finite impulse response filters

This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.

Phase-locked loop with filtered quantization noise

RF communication systems that provide combined demodulation and despreading are provided herein. In certain embodiments, an RF communication system generates an in-phase (I) signal and a quadrature-phase (Q) signal based on processing a received spread spectrum signal carrying a sequence of data symbols. The data symbols each have a symbol period and are coded by one or more multi-bit spreading codes. The RF communication system includes a symbol correlator that delays the I signal and the Q signal by an integer number of symbol periods to thereby generate a delayed I signal and a delayed Q signal, respectively. Additionally, the symbol correlator generates a correlation signal based on correlating the delayed I signal to the I signal and correlating the delayed Q signal to the Q signal. The RF communication system processes the correlation signal to recover the sequence of data symbols.

Combined demodulator and despreader

Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.

Feedforward phase noise compensation

Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

Systems and methods for clock and data recovery

Apparatus and method for acquiring and tracking a data signal are disclosed. Two different CDR circuits are configured to acquire and track data based on two different modulation schemes. While in the acquisition mode, the first CDR circuit may acquire data signal by sampling the signal at a reduced clock rate and handover to the second CDR circuit when a preamble is found. Also in the acquisition mode, the data acquisition and tracking circuit may determine the power level of the preamble signal and dynamically adjust the threshold level for the tracking period upon finding of the preamble.

Apparatus and method for modular signal acquisition and detection

Image rejection calibration includes initializing the calibration mode by applying to quadrature mixers, in place of the wanted RF input, an RF source in the frequency range of the wanted RF input, sensing the power output from the poly-phase filter, developing gain adjust and phase adjust correction values in response to the power output and adjusting in accordance with the correction values the gain of the quadrature signals from the quadrature mixers to the poly-phase filter and the phase of local oscillator quadrature signals from the local oscillator to the quadrature mixers to reduce the power output.

Image rejection calibration system

Embodiments of a system for calibrating the image rejection of a receiver include an image-rejection correction circuit that modifies the gain and phase of a first channel of a baseband image signal. The image-rejection correction circuit may include a summing circuit and first and second variable-gain elements. In one implementation, a filter receives a corrected first channel from the image-rejection correction circuit and an unmodified second channel of the image signal, while a controller analyzes power measured at the output of the filter, and adjusts the variable-gain elements to reduce the power of the image signal.

Image calibration and correction for low-IF receivers

An FSK demodulator system with tunable spectral shaping including a pair of quadri-correlators responsive to first and second quadrature signals, one of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at even integer multiples of the frequency deviation and for resolving the modulated FSK data represented by the quadrature signals and the other of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at odd integer multiples of the deviation frequency and for resolving the modulated FSK data represented by the quadrature signals, and a delay control circuit for setting a delay to each of the pair of quadri-correlators to control the first and second signals representative of the frequency deviation of the quadrature signals derived by each of the pair of quadri-correlators and generate a tuned spectral response at both even and odd integer multiples of the frequency deviation.

FSK demodulator system and method

A digital frequency measurement system including first and second digital differentiators responsive to first and second digital quadrature signals representative of first and second quadrature modulated input signals that represent binary data having a center frequency equal to a predetermined IF frequency for generating first and second differentiated signals, first and second processing circuits responsive to the first and second digital quadrature signals representative of the modulated input signals and the first and second differentiated signals for multiplying the first differentiated signal by the second quadrature digital representation of the input signals and multiplying the second differentiated signal by the first quadrature digital representation of the input signals to provide first and second multiplied signals, a combining circuit responsive to the first and second multiplied signals for generating a density signal having a pulse density proportional to the frequency of the input signals, a digital filter responsive to the density signal for providing an output signal representing the average value of the pulse density, and an envelope detector circuit responsive to the output signal for determining the midpoint of the maximum and minimum signal level representative of the input signals and providing a digital signal that represents the center frequency of the input signals.

Digital frequency measurement system and method with automatic frequency control

A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

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Glounthaune, Ireland

Philip Eugene Quinlan