Advanced Micro Devices Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Global Founderies Inc.

Philip Enrique Madrid

William Alexander Hughes

Vydhyanathan Kalyanasundharam

Derrick R Meyer

Tahsin Askar

Stephen C Ennis

Scott A White

Kiran Bondalapati

Wade L Williams

Brian W Amick

Shawn Searles

Benjamin T Sander

Michael T Clark

Guhan Krishnan

Roger Dwain Isaac

Gregory William Smaus

William McGee

Hanwoo Cho

Ryan J Hensley

Anand Daga

Ajay Naini

Sanjay Sethi

Deriick R Meyer

Michael A Comai

A dynamic random access memory (DRAM) includes first and second data buses, and first and second command and address (C/A) buses. The first data bus conveys a write data to the DRAM. The second data bus conveys read data from the DRAM. The first and second C/A buses are respectively associated with the first and second data buses. In one embodiment, the first data bus conveys the write data to a first bank of memory of the DRAM simultaneously as the second data bus conveys the read data from a second bank of memory of the DRAM. In another embodiment, the first data bus conveys the write data to a first rank of memory of the DRAM simultaneously as the second data bus conveys read data from a second rank of memory of the DRAM.

Dynamic random access memory (DRAM) bandwidth increase without per pin bandwidth increase

A method for throttling a bus, e.g. a memory bus, may be used to compensate for potential inaccuracy of feedback information received for monitored characteristics, e.g. temperature, reported by sensors configured in monitored devices, e.g. memory devices, accessed through the bus. For example, in case of a memory bus, a memory controller may be configured to throttle the memory bus in a way that maximizes system performance while ensuring that the memory devices keep operating within their thermal limits. Readings obtained from the memory, or from close proximity to the memory, may indicate whether the temperature of the memory has crossed over one or more designated trip points, and one or more algorithms may be executed to perform throttling according to the readings and based on fixed and dynamic throttling modes. The memory controller may infer temperature changes taking place in the memory devices when successive readings are indicating that the temperature of the memory device has remained over a given trip point. Based on these inferences, the memory controller may then change the manner in which the bus is throttled.

Temperature throttling mechanism for DDR3 memory

A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

Memory diagnostics system and method with hardware-based read/write patterns

Information of a first type is determined at an integrated circuit die of a data processing device included an integrated circuit package. The integrated circuit package includes the first integrated circuit die and a second integrated circuit die. Information of a second type is determined at the integrated circuit die. The first and second type of information is transmitted from the integrated circuit die to another integrated circuit die using a time-divided multiplexed protocol by transmitting the first information during a first time slot of the protocol and transmitting the second information during a second time slot of the protocol.

Data processing interface device

A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Device and method for transferring data between devices

A dynamic random access memory (DRAM) controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128-bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a 'copy' of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the basic input/output system (BIOS) has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.

Optimal solution to control data channels

In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

Shared resources in a chip multiprocessor

A system includes a processor coupled to a memory through a memory controller. The memory controller includes first and second queues. The memory controller receives memory requests from the processor, assigns a priority to each request, stores each request in the first queue, and schedules processing of the requests based on their priorities. The memory controller changes the priority of a request in the first queue in response to a trigger, sends a next scheduled request from the first queue to the second queue in response to detecting the next scheduled request has the highest priority of any request in the first queue, and sends requests from the second queue to the memory. The memory controller changes the priority of different types of requests in response to different types of triggers. The memory controller maintains a copy of each request sent to the second queue in the first queue.

Memory controller prioritization scheme

A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open. If the page is not closed as a result of the determination and/or prediction, it may be left open and closed after it has remained idle a specified length of time following the last access to the page.

Detection of speculative precharge

In one embodiment, an integrated circuit comprises first circuitry; a first clock generator coupled to supply a first clock to the first circuitry, and a control unit coupled to the first clock generator. The first clock generator is coupled to receive an input clock to the integrated circuit and is configured to generate the first clock. The control unit is also coupled to receive a trigger input to the integrated circuit. During a test of the integrated circuit, the control unit is configured to cause the first clock generator to generate the first clock at a first clock frequency, The control unit is configured to cause the first clock generator to generate the first clock at a second frequency greater than the first clock frequency for at least one clock cycle responsive to an assertion of the trigger input.

Shrink test mode to identify Nth order speed paths

In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor cores to other devices in a computer system. The node controller comprises a circuit coupled to receive the communications from the processor cores. In a redundant execution mode in which at least a first processor core is redundantly executing code that a second processor core is also executing, the circuit is configured to compare communications from the first processor core to communications from the second processor core to verify correct execution of the code. In some embodiments, the processor cores and the node controller may be integrated onto a single integrated circuit chip as a CMP. A similar method is also contemplated.

Core redundancy in a chip multiprocessor for highly reliable systems

A delay-locked loop (DLL) has a counter that is incremented or decremented by the loop in the process of achieving lock. The counter value is converted using an digital to analog converter (DAC) to an analog voltage that controls the delay through the delay line. During faster lock modes, the loop increments/decrements intermediate bits of the counter (with the bits less significant being held at a constant value, e.g., 0) to provide a coarse lock, rather than incrementing/decrementing the least significant bit of the counter. After coarse lock is achieved, a better lock is then achieved by incrementing/decrementing the counter using a smaller increment, i.e., a less significant bit is updated, until finally, the LSB is utilized to achieve fine lock. Utilizing the coarse lock first, and then one or more finer locks, allows the lock to be achieved more quickly.

Growing community of inventors

Austin, TX, United States of America

Philip Enrique Madrid