Motorola Corporation

Motorola Solutions, Inc.

Freescale Semiconductor,inc.

Arris Enterprises LLC

Philip E May

Kent Donald Moat

Raymond Brooke Essick, Iv

James M Norris

Brian Geoffrey Lucas

Silviu Chiricescu

Michael Allen Schuette

Ali Saidi

Michael D Pearce

Daniel Aaron Law

Kang Bum Lee

Shwetal S Parikh

William C Moyer

Trent J Miller

Steven D Tine

Juana Elias Nakfour

Brian Jeffrey Lucas

Kent D Moat

A data analytics system. The data analytics system includes a communication processor configured to communicate with one or more remote electronic devices, and one or more electronic processors electrically coupled to the communication processor. The one or more electronic processors are configured to receive a first data from the one or more electronic devices, generate a determination including a first confidence level based on the first data, identify additional data which would increase the first confidence level; request the additional data, receive responses including the additional data, and generate a second confidence level of based on the second data.

Data analytics system

Methods and systems for differentiating an object in a video. One system includes an electronic computing device including an electronic processor configured to determine context information associated with a video. The electronic processor is further configured to determine an object included in the video to be differentiated from other objects included in the video. The electronic processor is further configured to determine a level of differentiation for the object based on the context information. The electronic processor is further configured to alter the video to create an altered video that shows the object differentiated from the other objects in accordance with the level of differentiation. The electronic processor is further configured to provide the altered video to a display.

Methods and systems for differentiating one or more objects in a video

Methods and systems for correlating cross-feed of audio and video. One system includes a display and an electronic processor connected to the display. The electronic processor is configured to receive a plurality of videos and a plurality of audio feeds, present an initial arrangement including one or more of the plurality of videos on the display, and generate a soundscape based on the initial arrangement, the soundscape including one or more of the plurality of audio feeds. The electronic processor is further configured to determine which of the videos of the plurality of videos contains a predetermined item of interest, determine which of the audio feeds of the plurality of audio feeds contains audio associated with the predetermined item of interest, and adjust the initial arrangement and the soundscape to highlight the predetermined item of interest.

Correlated cross-feed of audio and video

A method and device for dispatching data carrier devices is provided. The device comprises: a communication interface; and a controller. The controller is configured to: receive, using the communication interface, an incident report including a location of an associated incident; determine from the incident report: that the location has limited wireless coverage; and information that is to be transported to the location of the associated incident; identify a data carrier device that is capable of transporting the information to the location and is one or more of: presently storing at least a portion of the information; and capable of downloading any portion of the information that is not presently stored at the data carrier device; and transmit, using the communication interface, a dispatch command to the data carrier device to travel to the location; and an indication of the information to be transported to the location.

Method and device for dispatching data carrier devices

A method and apparatus for providing a service at an incident scene is provided herein. During operation, a device will enter a geographic area (e.g., an incident scene), join a local-area network (LAN), and determine what services are presently being offered by other devices on the LAN. From a list of services deployed on the device, a determination is then made as to what services the device will run, and those services are then offered to all devices on the LAN.

Method and apparatus for providing services to a geographic area

A video tagging method, a video analytics method, and a Computer Assisted Dispatch (CAD) system use incident reports for video tagging and searching. A CAD system is integrated with field-based video surveillance systems to aid in searching video content and subsequent tagging of the video content. The systems and methods can include extracting keywords from a CAD incident report and creating a small, focused, and incident-specific dictionary on which to perform video searching in real-time. The small, focused, and incident-specific dictionary increases tagging accuracy and reduces tagging processing time in the context of video analytics. Further, a multi-pass approach in real-time continually updates and disseminates to video cameras of interest the small, focused, and incident-specific dictionary as the CAD incident report is updated and as the incident of interest plays out.

Computer assisted dispatch incident report video search and tagging systems and methods

A method and apparatus that allocates bandwidth among wireless sensor nodes in wireless sensor groups in a wireless sensor network (WSN) is disclosed. The method may include forming a plurality of wireless sensor node groups from a plurality of wireless sensor nodes based on battery levels of the wireless senor nodes, allocating transmission time slots for the wireless sensor nodes in each of the wireless sensor node groups based on at least one channel quality metric, determining average battery levels for each of the wireless sensor node groups and average battery level of all of the wireless sensor nodes, determining differences between the average battery levels of each of the wireless sensor node groups and the average battery level of all of the wireless sensor nodes, wherein if any difference in the average battery levels is above a predetermined threshold, regrouping the plurality of wireless sensor nodes according to the battery levels of the plurality wireless sensor nodes to minimize any variance in average battery level across all of the wireless sensor node groups.

Method and apparatus for battery-aware dynamic bandwidth allocation for groups of wireless sensor nodes in a wireless sensor network

A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor. When a specified number of data values have been produced by a particular sink, no more data values are produced by that sink. The instructions for the pipelined loop body may be repeated, without alteration, to eliminate prolog and epilog instructions.

Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters

A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. The sequence of instructions for a loop is compressed by identifying a set of aligned fields that contain NOP instructions in all of the control words of the sequence. The sequence of control words is then modified by removing the fields of the identified aligned set containing NOP instructions and adding an identifier that identifies the set of fields removed. The sequence of control words is processed by fetching the identifier at the start the loop, then, for each control word in the sequence, fetching a control word and reconstructing the corresponding uncompressed control word by inserting NOP instructions into the compressed control word as indicated by the identifier. The identifier may be a bit mask and may used to disable memory units and processing elements for the duration of the loop to reduce power consumption by the processor.

Dataflow graph compression for power reduction in a vector processor

Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

Data processing system using multiple addressing modes for SIMD operations and method thereof

A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.

Queuing cache for vectors with elements in predictable order

A re-configurable, streaming vector processor () is provided which includes a number of function units (), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch () and a micro-sequencer (). The re-configurable interconnection switch () includes one or more links, each link operable to couple an output of a function unit () to an input of a function unit () as directed by the micro-sequencer (). The vector processor may also include one or more input-stream units () for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface () to the host processor. The vector processor also includes one or more output-stream units () for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model. The instructions stored in a memory, in the sequence that direct the re-configurable interconnection switch, form a second part of the programming model.

Streaming vector processor with reconfigurable interconnection switch

A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Scheduler of program instructions for streaming vector processor having interconnected functional units

A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

Growing community of inventors

Palatine, IL, United States of America

Philip E May