Massana Research Limited

Agere Systems Inc.

Analog Devices International Unlimited Company

Analog Devices Global Unlimited Company

Pepperl+fuchs Se

Masaana Research Limited

Agere Systems (ireland) Research Limited

Philip Curran

Carl Murray

Alberto Molina Navarro

Stephen Bates

Albert Molina

Ciaran McElroy

Brian Paul Murray

Steffen Graber

Vincent Berg

Michael Martin McCarthy

Jacobo Riesco-Prieto

Brian Murray

Mark Dunn

Paul Costigan

Carl Damien Murray

Systems and methods are provided for performing operations comprising: accessing, by a transmitter physical layer (PHY) controller, data for transmission to a receiver PHY controller over a network connection; randomizing a delimiter independently of randomizing the data; selecting a disparity reset value based on the randomized delimiter to generate an initial miming disparity; encoding the randomized data based on the initial running disparity; generating a frame that includes the encoded randomized data and the randomized delimiter; and transmitting the frame from the transmitter PHY controller to the receiver PHY controller.

Method to reduce the effect of fixed stream delimiters on emissions and receive filter training

This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

Method to improve latency in an ethernet PHY device

In a 1000 BASE-T transceiver, a timing error detector (TED,) receives its inputs directly from the output of an ADC () and from a decision device (). Timing recovery is acquired in three stages: a non-decision directed (NDD) stage during which only the output of an ADC () are used for acquisition; a stage for acquiring the remote scrambler and predicting symbols; and a decision-directed (DD) stage during which locally predicted symbols are also used for acquisition. Because the timing error detector (TED,) does not take inputs from the FFE () there is no information about cable length, and so an input of gain from an AGC is used to indicate cable length.

Timing recovery in data communication circuits

Channel equalization in a 1000BASE-T receiver is performed by a fixed mode analog filtersuitable for the longest possible cable length, by a FFE (), and by a digital filter. The digital filter () has two sets of taps. One set is optimal for shorter cable lengths and so cancels adaptation for long cable lengths and assists operation of the analog filter. A decision block () selects an appropriate set of taps.

Channel equalization in data receivers

A receiver () has an equalizer () which introduces inter symbol interferance (ISI) in a controlled manner and low pass filters to reduce noise. The ISI is introduced and the noise is reduced by a filter () in an adaptation path. A trellis decoder () of the receiver () removes the ISI to avoid propagation error. It does this in front end modules (), outside of its critical path. There is a better decoder performance because noise is smaller.

Data receiver

A FIR filter in a Gigabit transceiver in which data words are represented in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs an input coefficient and the ZERO bit, an XOR gate XORs the SIGN bit and the output of the AND gate, and a multiplier left-shifts the coefficient using the SHIFT bit and the output of the XOR gate. The circuit has a very low gate count.

Processing of quinary data

A Gigabit transceiver () has a receiver () and a transmitter (). There is an ADC () in the receiver () for each channel (A, B, C, D). The ADCs () oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs () operate off half of the oversampling rate. In the receiver () fractionally spaced equalisers (FSES,) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.

Timing control in data receivers and transmitters

A data communication receiver comprises an equalizer for adapting to each of a plurality of channels to open the eye for each channel in a Gigabit (1000BASE-T) transceiver. The eye is open for a first channel (A) and a transformation process applies the coefficients of that adaptation to open the eye for the other dimensions. The transformation process keeps the magnitude response constant.

Compensation for interference in data receivers

A cancellation system comprises a channel circuit () for each noise source, such as echo in a particular cable pair. There are only eighty taps per channel, in two blocks (n_echo_a, f_echo_a). Each block is preceded by a variable delay line comprising blocks of registers cascaded so that a delay value of 0 to 40 clock cycles can be chosen. The delay value is determined by determining an optimum position for each tap block. This is achieved by determining a maximum coefficient sum for a number of windows. Taps from other channels are used during training, so that there is a total of 160 taps for each channel during training to enable the optimum positions to be determined.

Echo and crosstalk cancellation

A DSP coprocessor,is connected to a host sub-system (,). The host sub-system (,) has a host processor (,), a host RAM (,), and shared RAM banks (,). Multiplexers (,) provide access for either the DSP or the host to a shared RAM bank. Macro commands for functions of the DSP coprocessor are retrieved from the shared RAM banks. This allows comprehensive interaction of the host and the DSP coprocessor.

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Philip Curran