Westinghouse Electric Corporation

United States of America As Represented by the Secretary of the Air Force

Philip C Smith

John L Fagan

Teresa B Smith

A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder.The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

Programmable redundancy circuit

A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

A semiconductor device structure incorporating the edge of silicon island as a surface for diffusing impurities is described to form the drain and source of an MOS transistor and interconnections therebetween to form semiconductor devices such as MOS transistors, variable threshold MNOS transistors, row decoders for use in memories, memory arrays, interconnect crossovers, and high-voltage transistors. A semiconductor process is described for fabricating the above devices utilizing four or five masks. The invention overcomes the problem of high-density integrated circuits by utilizing the edges of silicon islands on an insulating substrate as well as the upper surface of the islands. In addition, contact metallizations are non-critical because of the Schottky barrier diode formed between aluminum and n-type silicon. Both n and p-type semiconductor devices are described.

Device structures for high density integrated circuits

A memory apparatus having a row and column decoder for controlling the read and write function to a transistor memory pair. A single power/chip select pad is utilized to both power the memory and select the memory chip. External control signals are applied directly to critical internal node within the memory apparatus.

Fast access non-volatile memory

An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

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Columbia, MD, United States of America

Philip C Smith