Digital Processing Systems, Llc.

At&t Bell Laboratories

Philip C Chao

Ronald J Canniff

Sam S-k Lee

Alan Howard Matten

Charles E Stroud

A method of rendering at least part of an image from an at least one external source into a two-dimensional memory array having integer x and y pixel coordinates based upon a set of integer coordinates of an outline of the rendered image. The method includes the steps of forming a parallelogram defined by a parallel series of effect lines forming an angle e with either the x or y axis of the memory array and bounded on opposing ends of the scan lines by a scan axis, the parallelogram surrounding at least part of the two-dimensional memory array and rendering the image from the at least one external source into the memory array while moving unidirectionally along the effect lines and scan axis using the outline coordinates as transition points for selection and non-selection of the image.

Method and apparatus of rendering a video image

An apparatus and method of editing video sequences. The method includes the steps of displaying a timeline of a video sequence on a timeline on a monitor of an editing computer, placing a movable cursor at a selected location along the timeline, displaying a miniaturized version of a video frame corresponding to the selected location of the timeline adjacent the timeline, and editing the video sequence based upon the displayed video frame.

Video and audio cursor video editing system

An arrangement where a plurality of digital signal processors cooperate in the performance of a digital signal processing function. The processors are interconnected by means of a synchronous network which provides time division multiplexed communication links between processors for communicating intermediate processing results therebetween. The synchronous network includes a plurality of port circuits each associated with one of the processors. The network generates timing signals defining frames of time slots and defining superframes comprising N frames. Each port circuit can control the transmission of digital data from a memory of its associated processor during M1 time slots of each superframe. Each port circuit can also control the writing of digital data to its associated processor during M2 time slots of each superframe. The value of N, the number of frames per superframe, is programmable. The values of M1 and M2 are also programmable for each port circuit.

Growing community of inventors

Naperville, IL, United States of America

Philip C Chao