Xilinx, Inc.

Disney Enterprises, Inc.

Philip Bryn James-Roxby

Eric R Keller

Ralph D Wittig

Gordon John Brebner

Chidamber R Kulkarni

Vinod Kumar Kathail

Shail Aditya Gupta

Samuel R Bayliss

Jeffrey Stroomer

Prasanna Sundararajan

Graham F Schelle

Brandon Blodget

Scott P McMillan

Henry E Styles

Christopher H Dick

Juan J Noguera Serra

Baris Ozgul

Kornelis Antonius Vissers

Jan Langer

Richard Lewis Walke

Daniel J Downs

Chia-Jui Hsu

Raul E Rangel

Paul R Schumacher

Sonal Santan

Michael E Attig

Derek R Curd

Eric F Dellinger

Sean Kelly

Goran H K Bilski

Akella Sastry

Fernando J Martinez Vallina

Sheng Zhou

Richard J LeBlanc

Vincent P Eck

Jeffrey M Fifield

Punit S Kalra

Devadas Varma

Austin H Lesea

Trevor J Bauer

Roger Brent Milne

Jonathan B Ballagh

L James Hwang

Michael Alan Baxter

Patrick Lysaght

Stephen Andrew Neuendorffer

Chidamber Kulkarni

Cameron D Patterson

Yi-Hua Edward Yang

Goran Hk Bilski

Jeffrey V Lindholm

Peter McColgan

Mukund Sivaraman

Paul M Hartke

Brendan K Bridgford

Christopher E Neely

Rishi Surendran

Ajit K Agarwal

Edward Richter

Charles Kwok-Wah Lo

Stephen W Trynosky

Charles A Ross

Russell J Morgan

Richard DeFelice

Robert M McGee

Charles Kwah-Wah Lo

Scott P Mcmillan

Brandon J Blodget

Yi-Hua E Yang

Kwok-Wah Lo

A computing node for a computing system includes a processor, conversion circuitry, and routing circuitry. The processor generates a data signal based on a function of an application executed by the computing system. The data signal has a first precision format and a first sparse representation. The conversion circuitry receives the data signal from the processor and generate a converted data signal by at least one of converting the first precision format to a second precision format and converting the first sparse representation to a second sparse representation. The routing circuitry transmits the converted data signal to switch circuitry of the computing system.

Dynamic data conversion for network computer systems

A disclosed compression method includes inputting a data set of floating point values from an input circuit to a compression circuit and detecting non-zero values and sequences of zero values in the data set. The compression circuit outputs, in response to detection of a non-zero value in the data set, the non-zero value to an output circuit. The compression circuit generates, in response to detection of a sequence of zero values in the data set, a subnormal floating point value having significand bits that indicate counted zero values in the sequence, and outputs the subnormal floating point value to the output circuit.

Lossless compression using subnormal floating point values

Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Control and reconfiguration of data flow graphs on heterogeneous computing platform

A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

Data processing engine arrangement in a device

The embodiments herein describe a conversion engine that converts floating point data into integer data using a dynamic scaling factor. To select the scaling factor, the conversion engine compares a default (or initial) scaling factor value to an exponent portion of the floating point value to determine a shift value with which to bit shift a mantissa of the floating point value. After bit shifting the mantissa, the conversion engine determines whether the shift value caused an overflow or an underflow and whether that overflow or underflow violates a predefined policy. If the policy is violated, the conversion engine adjusts the scaling factor and restarts the conversion process. In this manner, the conversion engine can adjust the scaling factor until identifying a scaling factor that converts all the floating point values in the batch without violating the policy.

Converting floating point data into integer data using a dynamically adjusted scale factor

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Dataflow graph programming environment for a heterogenous processing system

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.

Streaming interconnect architecture for data processing engine array

An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Compilation flow for a heterogeneous multi-core architecture

A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

Device with data processing engine array

An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

Heterogeneous multiprocessor platform targeting programmable integrated circuits

Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.

Methods and circuits for debugging circuit designs

System, method, and computer program product to perform an operation, including installing a first service on a first virtual machine and a second service on a second virtual machine in a web services cluster, testing the first service on the first virtual machine and the second service on the second virtual machine to determine that the first and second services are stable, installing the first service and the second service on a third virtual machine in the web services cluster, causing at least a portion of traffic directed to the first service and the second service to be sent to the third virtual machine, testing the first service and the second service on the third virtual machine, and removing the first and second virtual machines from the web services cluster upon determining that the first service and the second service executing on the third virtual machine are stable.

Safe low cost web services software deployments

There are provided systems and methods for providing low-risk deployment of a web service. In one implementation, such a method includes testing the web service on one or more virtual machines assigned to a testing environment of the system, and reassigning the one or more virtual machines to a production environment of the system configured to service live traffic for the web service. The method also includes hosting the web service using the same one or more virtual machines used to test the web service.

Low-risk deployment of web services

Growing community of inventors

Longmont, CO, United States of America

Philip Bryn James-Roxby