International Business Machines Corporation

Philip Braun Winterfield

David Arnold Luick

John Christopher Willis

Kenneth J Kiefer

Gabriel Mauricio Silberman

Michael Joseph Corrigan

Jaime Humberto Moreno

Kemal Ebcioglu

Larry Wayne Loen

Mahmut K Ebcioglu

Steven L Jones

Steven Michael Dickes

David Robert Russell, Jr

Dave A Luick

Steve R Kunkel

An object oriented storage pool provides enhanced performance by allowing very fast and efficient allocation of storage elements from the storage pool instead of obtaining a storage element from the heap in an object oriented computer system. The storage pool is preferably in a linked-list format, and operations on the linked list to allocate and return storage elements are atomic operations to assure serialization of accesses to the storage pool. The presence and operation of the storage pool is hidden from the user by overloading the New() and delete() methods that are defined in the programming language. In this manner the storage pool can be introduced without modification to existing application software, thereby enhancing computer system performance without changing other software in the system.

Object oriented storage pool apparatus and method

In a computer capable of executing a superscalar and a very long instruction word instruction wherein the computer has compiled a number of primitive operations that can be executed in parallel into a single instruction having multiple parcels and each of the parcels correspond to an operation, the invention is an improved instruction cache to store all potential subsequent instructions and a method to select the subsequent instruction when several possible branches of execution are probable and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of an instruction are replicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache having the same next address; individual instructions are identified by the replicated offset addresses. Further the instruction cache is divided into minicaches, each minicache to store one parcel, which allows rapid autonomous execution of each parcel. Simultaneously, all branch conditions are evaluated in parallel to determine the next instruction and all offset addresses are decoded in parallel. Only after the control flow or the branch taken, or the subsequent or next instruction is determined, are the results of that branch stored and the decoded addresses are used to late select the next instruction from the instruction cache.

Method and apparatus to select the next instruction in a superscalar or

A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a 'local coherence unit' and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a 'global coherence' unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared. The global coherence table also preferably indicates in which node a copy of the most current data resides.

Multiprocessor cache coherence directed by combined local and global

A method and apparatus estimate the memory address needed for a low level programming instruction in reduced instruction set computing systems. Taking advantage of a known computing environment and data architecture, bits from a displacement field in an Instruction Register may be combined with bits from a Base Register through hardware logic circuitry, preferably performing a mathematical computation such as addition. Together with bits gated directly from the Base Register and the displacement field, the combined bits form an estimate of the effective address of the desired memory location. The estimation is performed early in an instruction cycle, and therefore allows data from the memory, preferably a Data Cache, to be available at the end of the next instruction cycle, thus producing the address in what appears to be zero cycles. The method and apparatus avoid stall conditions from the CPU, and are particularly useful for Very Long Instruction Word architecture.

Pseudo zero cycle address generator and fast memory access

A very long instruction word (VLIW) architecture and method provide for functionally expanding a parcel. The instruction register of the VLIW architecture is divided into a plurality of parcels, each of which has corresponding processing logic. The processing logic performs various functions based on the data within the corresponding parcel. A single parcel, however, can only specify a limited number of functions or include a limited amount of data for processing such that the level of optimization for a given VLIW may be impeded. The selector logic and processing logic, however, allow for data from a non-corresponding parcel to be selected and processed. In this manner, the functions and/or amount of data for processing in a single parcel can be expanded by using data from a non-corresponding parcel.

VLIW architecture and method for expanding a parcel

Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.

Reordering of memory reference operations and conflict resolution via

A synchronous interrupt handler for a processing system executing multiple modes of operation employs a minimum number of lines of interrupt handler code written to execute at the 'zeroth' level, is combined with a virtualized interrupt vector table. An identical zeroeth level handler is inserted at each of the processor's interrupt vector entry pints. These short code sequences are the first to gain control following an interrupt. They are handwritten in the platform's native instruction set to be mode-independent. For example, if the platform's processor does not alter the 'endianness' of the machine state following an interrupt, the 'zeroeth level' code must be written for endian neutrality; likewise, for 32/64-bit mode, etc. For each mode of operation, there is created a Virtualized Vector Table to represent the proper interrupt handlers for each physical interrupt level. Each task data structure, implicitly reflecting its unique mode of operation, contains a pointer to its virtualized vector table. The zeroeth-level handlers then extract the virtualized vector table reference for their own interrupt level and indirectly pass control to the preloaded table value.

Integrating multi-modal synchronous interrupt handlers for computer

A method and apparatus for reordering memory operations in superscalar or very long instruction word (VLIW) processors is described, incorporating a mechanism that allows for arbitrary distance between reading from memory and using data loaded out-of-order, and that allows for moving load operations earlier in the execution stream. This mechanism tolerates ambiguous memory references. The mechanism executes only one additional instruction for disambiguation purposes, thus producing good performance, and integrates memory disambiguation with speculative execution of instructions. The overhead introduced is only one instruction, and the load operation can be arbitrarily moved earlier in the instruction stream. The mechanism can cope with conflicts that occur as a result of an unexpected combination of store/load instructions, can be used in a coherent multiprocessor context, and combines speculative execution with reordering of memory operations in a way which requires simple hardware support.

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Rochester, MN, United States of America

Philip Braun Winterfield