Intel Corporation

Phil W Martin

Nelson L Yaple

Jonathan C Lueker

Scott B Blum

Steven D Kassel

Alan Packer

Craig D Cedros

Greg A Peek

Gary A Alvstad

Dave Chalupsky

A method is presented that may reduce the number of I/O transactions needed to transfer data between a host device and peripheral device over a parallel port. According to one embodiment, only two I/O transactions are needed to transfer a byte of data as opposed to the eight I/O transactions need in the IEEE 1284-1994 standard. During the two I/O transactions (e.g., transferring data from the host device to the peripheral device), the host device places the data on the data signal lines of the parallel port and toggles a signal on one of the control signal lines. In response, the peripheral device reads the data from the parallel port. Additional bytes can be sent by placing the data onto the port and toggling the signal on the same control signal line. Using this method, a data rate of approximately 4 Mega bits per second may be achieved.

Method and apparatus for increasing the data rate over a parallel port

In one embodiment of the invention, an access point for use in a powerline based network includes first physical layer circuitry to interface with a powerline and second physical layer circuitry to interface with an antenna. The access point also includes circuitry to interface between the first and second physical layer circuitry. The first and second physical layer circuitry and the circuitry to interface between the first and second physical layer circuitry allow an untethered electrical device to have data communication through the powerline with an electrical device tethered to the powerline. Under another embodiment of the invention, a powerline based network includes a powerline and an access point connected to the powerline and capable of wireless communication.

Wireless LAN segments with point coordination

A method and apparatus to optimize buffer memory management in a computer system communications resource. The present invention decreases the time for receiving data from and transmitting data to a network by providing for receipt and transmittal of a data packet, prior to the data packet being in a communications resource buffer memory. Consequently, data spends less time in the communications resource buffer memory. This allows a communications resource to handle more data without increasing the size of its buffer memory and to increase the effective data transfer rate. The present invention provides a means for: 1) starting the transmission of data into the network before all data has been transferred to buffer memory in the communications resource, 2) beginning the transfer of data from the buffer memory of the communications resource before the complete data packet has been received and stored in buffer memory, and 3) error checking to insure data integrity.

System for transferring portion of data to host from buffer if size of

A method and apparatus for automatically resolving I/O address conflicts among hardware adapters coupled to a common bus in a computer system. System I/O software tests each address space of a set of possible automatic conflict resolution (ACR) adapter address spaces for bus conflicts between the ACR adapters and non ACR adapters. For each address space having a conflict, the system I/O software shifts the address spaces of the ACR adapters to a next sequential address space of the set of possible address spaces. Thereafter, the system I/O software reallocates the address space of each ACR adapter, such that the address spaces of the ACR adapters do not overlap, and are not in conflict with the non ACR adapters.

Automatic input/output address conflict resolution

A method of selecting a free interrupt request level (IRQ) from a multiplicity of IRQs for assignment to a device being added to a computer system. Selection begins by identifying a first set of probably free IRQs from the multiplicity of IRQs. Afterward, actually free IRQs are identified from the first set of probably free IRQs. Finally, an IRQ that is least likely to be requested is selected from among the actually free IRQs circuitry for selecting a free IRQ is also described. Circuitry for selecting a free IRQ within a computer system having a multiplicity of IRQs is also described. The circuitry includes circuitry for identifying a first set of probably free IRQs from the multiplicity of IRQs, circuitry for identifying a second set of actually free IRQs from the first set of probably free IRQs, and circuitry for selecting as the free IRQ a first IRQ a one of the actually free IRQs that is least likely to be requested.

Growing community of inventors

Banks, OR, United States of America

Phil W Martin