Topside Research, LLC

Phil Terry

Michael J De La Garrigue

Chris Haywood

Bao K Vuong

Thomas C Reiner

Yaxin Shui

Adam Rappoport

Kirk Jong

Kevin Robertson

Neely Walls

Quang Hong

There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned.

Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices

A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.

Network processor having bypass capability

Growing community of inventors

Simi Valley, CA, United States of America

Phil Terry