Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Other

Phil Reusswig

Sahil Sharma

Niles Yang

Rohit Sehgal

Nian Niles Yang

Grishma Shah

Piyush Anil Dhotre

Mohan Dunga

Gautam Ashok Dusija

Deepak Raghu

Sarath Chandran Puthenthermadam

Dmitry Vaysman

Pitamber Shukla

Joanna Lai

Alexandra Bauche

Yosief Ataklti

Piyush Dhotre

Mohsen Purahmad

A data storage device includes a non-volatile memory device having one or more memory dies and each of the memory dies include a plurality of input-output (I/O) lines. The data storage device further includes a controller. The controller is configured to receive an instruction to enter a low-power operating mode. Entering the low-power operating mode includes removing power from the one or more memory dies, providing an output signal toggling between a logic high and a logic low at a predetermined frequency to the plurality of I/O lines for a predetermined period of time, and operating in the low-power operating mode upon the expiration of the predetermined period of time.

Data storage device with enhanced power mode management

A data storage system includes a storage medium and a storage controller configured to perform interface training operations. The interface training operations include loading a test data pattern into a first controller buffer of the storage controller, loading the test data pattern into a first storage medium buffer of the storage medium, setting a first read voltage or timing parameter at the storage controller, transferring the test data pattern from the first storage medium buffer to a second controller buffer of the storage controller using the first read voltage or timing parameter, comparing the test data pattern in the first controller buffer with the test data pattern in the second controller buffer, and determining a first read transfer error rate based on the first comparison.

Storage medium-assisted system interface training scheme

A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Storage system and method for boundary wordline data retention handling

A memory controller includes, in one implementation, a host interface, a memory interface, and a flash translation layer (FTL). The FTL is configured to receive a request from a host device to store data in a zone of a solid-state memory. The FTL is also configured to determine a zone reset rate classification as one of a hot classification, a cold classification, and a normal classification. The FTL is further configured to allocate the zone to a memory die with the fewest free die blocks when the zone reset rate classification is the hot classification. The FTL is also configured to allocate the zone to a memory die with the most free die blocks when the zone reset rate classification is the cold classification. The FTL is further configured to send the data to the memory die for storage therein.

Zone allocation for data storage device based on zone reset behavior

A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.

Detection of a last programming loop for system performance gain

Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.

Storage device parameter monitoring for load balancing

A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell ('SLC') memory cells or multi-level cell ('MLC') memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the &#x201c;nominal&#x201d; programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.

Non-volatile storage system with fast SLC operation

A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

Erase suspend scheme in a storage device

Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

Method of identifying and preparing a key block in a flash memory system and memory controller therefor

A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Adaptive read trim for second read data retention

Disclosed is an apparatus including a memory device. The memory device includes a memory array, a number of non-volatile memory sections configured to store a copy of operational information for the memory array, and a controller coupled to the number of non-volatile memory sections. The controller can responsive to a first wake-up operation, select a first non-volatile memory section as a starting section to retrieve the copy of operational information. The controller can responsive to a second wake-up operation, select a second non-volatile memory section as the starting section to retrieve the copy of operational information without regard to success of a prior attempt to retrieve the copy of operational information.

Systems and methods to wake up memory array

Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.

Performance of a read in a memory system

In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool transfer criteria, refraining from reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool.

Balancing the block wearing leveling for optimum SSD endurance

In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Method and system for improving performance of a storage device using asynchronous independent plane read functionality

A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.

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Mountain View, CA, United States of America

Phil Reusswig