Samsung Electronics Co., Ltd.

Phil Ouk Nam

Seulye Kim

Jaeyoung Ahn

Hong Suk Kim

Sung Gil Kim

Ji Hoon Choi

Jae Young Ahn

Junkyu Yang

Ji-Hoon Choi

Sunggil Kim

Jung Ho Kim

Kihyun Hwang

Dongchul Yoo

Han Jin Lim

Woosung Lee

HongSuk Kim

Yong-Hoon Son

Sangsoo Lee

Woong Hee Lee

Kyunghyun Kim

JinGyun Kim

Daehong Eom

Yeon-Sil Sohn

Chaeho Kim

Chang Seok Kang

Sung Yun Lee

Kwangchul Park

Wonbong Jung

Chang Sup Lee

Byeongju Kim

Woonkyung Lee

Jaegoo Lee

Junggeun Jee

Jin-I Lee

Juhyung Kim

JongHeun Lim

Hyung Joon Kim

Kyung Hyun Kim

Yong Hoon Son

Jintae Noh

Dongkyum Kim

Woojin Jang

Gukhyon Yon

Byong-Hyun Jang

Sunghae Lee

Jin Il Lee

Hunhyeong Lim

Sang Yub Ie

Youngseon Son

Kwang Chul Park

Tae Yong Kim

Won Bong Jung

Byeong Ju Kim

Jae Hyun Yang

Yeon Sil Sohn

Jin-l Lee

Byong-hyun Jang

Kwangyoung Lee

Jong Heun Lim

A semiconductor manufacturing apparatus including a process chamber and a boat having a support member supporting substrates arranged in a first direction. An inner tube encloses the boat and includes a slit along a side wall. A nozzle supplies a process gas and includes a gas injection port at a position corresponding to the slit. The gas injection port includes a first inlet and first outlet. The slit includes a second inlet and second outlet. A distance to an end of the first inlet from a center line that connects a center of the first inlet and a center of the second outlet is different from the distance from the center line to an end of the first outlet and/or a distance from the center line to an end of the second inlet is different from a distance from the center line to an end of the second outlet.

Semiconductor manufacturing apparatus

A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

Three dimensional semiconductor device and method of forming the same

A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

Vertical memory device with a channel layer in a stacked dielectric layer

Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

Three-dimensional semiconductor memory device

A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

Semiconductor device and method of fabricating the same

A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

Three-dimensional semiconductor devices

Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.

Three-dimensional semiconductor device and method of fabricating the same

The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

Semiconductor memory devices and methods for fabricating the same

Semiconductor device including dielectric layer

A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

Semiconductor memory device

Growing community of inventors

Suwon-si, South Korea

Phil Ouk Nam