Samsung Electronics Co., Ltd.

Phil-Jae Jeon

Doh-Young Kim

Woo-seok Kim

Dong-Uk Park

Sang-Woo Pae

Myoung-Su Lee

Da Rae Ahn

Hye-Won Shim

A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

Clock switch device and system-on-chip having the same

A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit. The clock generation unit generates a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit. The mirror delay unit outputs a plurality of delayed preamble signals based on the preamble signal during a preamble period. The preamble phase detection unit provides the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period. The sampling unit extracts data from the data signal by sampling the data signal with the clock signal.

Clock and data recovery circuit and method of recovering clocks and data

A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.

Lock detector and delay-locked loop having the same

A clock generator based on a phase-locked loop with one pole and an improved period jitter characteristic is disclosed. The clock generator comprises a phase detector for generating a phase detection signal and a phase error signal, a charge pump for generating a loop control voltage, a loop filter for generating an integrated voltage signal, a voltage-controlled oscillator for generating multi-phase output signals, and a phase error compensating circuit for compensating a phase error generated at a prior input clock. The clock generator has an improved period jitter characteristic by compensating a phase error generated at a prior input clock.

Clock generator with one pole and method for generating a clock

A phase-locked loop circuit including a lock detection function is disclosed. The phase-locked loop circuit comprises a lock detection circuit. The lock detection circuit includes a lock-detection-start-signal generator, a lock-detection-clock generator, and a lock-detection-signal generator. The lock-detection-start-signal generates a lock detection start signal when the pulse width of an up signal and a down signal reaches a predetermined value. The lock-detection-clock generator generates a lock detection clock signal on the basis of the up signal and the down signal. The lock-detection-signal generator counts the lock detection clock signal, and generates the lock detection signal. The phase-locked loop circuit is capable of discriminating the operating regions thereof and outputting a lock detection signal when the locking of phase is completed.

Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof

A delay-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled delay line and a coarse lock detector. The phase frequency detector generates an up signal and a down signal corresponding to phase and frequency differences between an input clock signal and a feedback signal. The charge pump receives the up signal, the down signal and a coarse lock detection signal to generate a current signal. The loop filter receives and filters the current signal through a low-pass filter to generate a direct voltage signal. The voltage controlled delay line receives the input clock signal and the direct voltage signal to generate the feedback signal and control signals. The coarse lock detector receives the control signals to generate the initialization signal and the coarse lock detection signal to adjust Td within Tin/2&#x3c;Td&#x3c;2&#xd7;Tin when Td&#x2267;2&#xd7;Tin or Td&#x2266;Tin/2.

Delay-locked loop circuit and method thereof for generating a clock signal

A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

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Osan-si, South Korea

Phil-Jae Jeon