Hynix Semiconductor Inc.

Phil-Goo Kong

Kuk-Han Yoon

Sung-Kwon Lee

Jin-Ki Jung

Sang-Ik Kim

Kwang-Ok Kim

Myung-Kyu Ahn

Il-Young Kwon

Jae-Young Kim

Sung-Chan Park

Jin-Sung Oh

Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method including forming many conductive layer patterns on a substrate, forming an interlayer insulating layer on a resulting structure where the conductive layer patterns are completed, exposing a conductive layer pattern which at least one sidewall of a contact region between conductive layer patterns is neighboring the contact region, and forming an insulating spacer on the sidewall of the exposed conductive layer pattern.

Method for forming contact hole and spacer of semiconductor device

A method for fabricating a semiconductor device capable of minimizing deformations of a photoresist pattern and losses of a hard mask. The method includes the steps of: forming an insulating layer for a hard mask on an etch-target layer; forming a sacrificial layer on the insulating layer; forming a photoresist pattern on the sacrificial layer; forming at least one sacrificial hard mask by etching the sacrificial layer with the photoresist pattern as an etching mask; forming the hard mask by etching the insulating layer with the sacrificial hard mask as an etching mask; and forming a predetermined number of patterns by etching the etch-target layer with use of the sacrificial hard mask and the hard mask as etching masks.

Method for fabricating semiconductor device

Growing community of inventors

Ichon-shi, South Korea

Phil-Goo Kong