Oak Technology, Inc.

Other

Phares J Grey

Shengquan Wu

Christopher T Brown

Method and system for optimally estimating the location of each of a sequence of two or more synchronization patterns in a digital signal bit stream. A first reference location for a sync pattern is determined. A Boolean product or other product of the sync pattern (of length S) with S consecutive bit values of the digital stream is formed, for each of a selected consecutive sequence of candidates for a second reference location of the sync pattern within a window of selected length. A candidate reference location that yields the largest (or smallest) product value within the window is estimated to be a second or &ldquo;next&rdquo; reference location of the sync pattern, if the product value is at least equal to (or, alternatively, is no greater than) a selected threshold value. The sync pattern used for testing the digital stream can be varied from one location to another. The number of bit matches or the number of bit non-matches can be used to determine an optimal reference location for the sync pattern.

Optimal location of a digital sync pattern

Under current CD-R and CD-RW technology, whenever a present mark is burned onto a CD, only the dimension of the present mark is considered in controlling the heat source (e.g. a laser). The present invention improves upon the current technology by taking into account not only the dimension of the present mark but also the effects on the present mark due to the marks and spaces within relatively close proximity to the present mark. By doing so, the present invention significantly improves the accuracy of the writing process. This in turn enables the present invention to eliminate the writing errors of the prior art.

Method and apparatus for controlling the writing of information onto a storage medium

A circuit and method for selectively and dynamically delaying a signal is presented. A series of delay modules are used to provide progressively finer delays. A multiplexer is used after each delay module to select one of a plurality of signals to pass on to a subsequent delay module. Each multiplexer is controlled by a control signal which can vary in time so that different delays can be selected for different portions of the signal to be delayed. By providing the proper control signals to the multiplexers any delay corresponding to a sum of the available individual delays generated by the individual delay modules is possible. The circuit and method are particularly useful for imposing individual delay times on the pulses in a logic level signal.

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Milpitas, CA, United States of America

Phares J Grey