Cadence Design Systems, Inc.

Rambus Inc.

Phalguni Bala

Kiran Baby

Sudhir Kumar Katla Shetty

Ashwin S M

Navin Kumar Mishra

Younus Syed

Vinod Kumar

Hajee Mohammed Shuaeb Fazeel

Anirudha Shelke

Manjunath Karikatti

Gaurav Pradeep Bhojane

Embodiments included herein are directed towards a skew-tolerant, glitch-free multiplexer circuit. The circuit may include a first flip-flop configured to receive a gate signal and to generate an output. The circuit may further include auto-burst detection circuitry having second and third flip-flops. The auto-burst detection circuitry may be configured to receive the output at the second flip-flop and to generate an auto-burst detection circuitry output from the third flip-flop. The circuit may also include a plurality of flip-flops configured to receive the auto-burst detection circuitry output, wherein each of the plurality of flip-flops is configured to provide an input to a multiplexer.

System and method for skew-tolerant, glitch-free multiplexing with auto-strobe burst detection

Embodiments included herein are directed towards a passive equalization circuit. The circuit may include a transmitter, a receiver; and a passive equalization circuit that may be located between the transmitter and the receiver. A first inductor may be located between the transmitter and a primary node net, and a second inductor may be located between the primary node net and a pad, and a third inductor may be located between the primary node net and the receiver.

Passive equalization circuit

A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (&#x3c0;) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.

High-bandwidth signal driver/receiver

In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique.

Receiver training of reference voltage and equalizer coefficients

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Phalguni Bala