Adeia Semiconductor Bonding Technologies Inc.

Pacific Biosciences of California, Inc.

Western Digital (fremont), Inc.

Silicon Laboratories Inc.

Silicon Clocks, Inc.

Georgia Tech Research Corporation

Jds Uniphase Corporation

Pezhman Monadgemi

Cyprian Emeka Uzoh

Charles Gerard Woychik

Terrence Caskey

Michael W Newman

Belgacem Haba

Roger T Howe

Emmanuel Philippe Quevy

Stephen Wilson Turner

Lei Wang

Fatima Lina Ayatollahi

Ravi Saxena

Denis Zaccarin

Ilyas Mohammed

Paul M Lundquist

Annette Claire Grot

Ellis Chau

Reynaldo Co

Cheng Frank Zhong

Mathieu Foquet

Sergey Savastiouk

Aaron J Rulison

Zongrong Liu

Se Young Yang

Valentin Kosenko

Peiqian Zhao

Gregory Kearns

Yanqiao Huang

Ron Kuse

Drew Martinez

Edward Lee McBain

Farrokh Ayazi

Jay A Skidmore

Vincent V Wong

Prasad Yalamanchili

Mina Raieszadeh

Erik Paul Zucker

Reddy Raju

Frank Zhong

Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.

Nanoscale apertures having islands of functionality

An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

Method and structures for heat dissipating interposers

A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

BVA interposer

An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/&#xb0; C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.

Method for fabricating a carrier-less silicon interposer

Processes for making high multiplex arrays for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. The high multiplex arrays include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination.

Process for making high multiplex arrays

Structures for heat dissipating interposers

A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Thin wafer handling and known good die test method

Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Metal PVD-free conducting structures

Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Methods and structure for carrier-less thin wafer handling

To fabricate an interposer for interfacing waveguides (e.g. optical fiber cables) to transducers, a cavity (410) is formed in a top surface of a substrate. A first layer (520) is formed over the cavity's bottom surface, with one or more gaps in the first layer's top surface. A second layer (3410) is formed in the one or more gaps. The second layer overlaps the first layer. At least part of the first layer is removed to form channels separated from each other by portions of the second layer that are located in the one or more gaps; at least part of the first layer is removed from under the second layer. The second layer portions in the one or more gaps provide one or more spacers in the cavity; these one or more spacers at least partially cover the channels. Waveguides can be placed into the channels.

Structures formed using monocrystalline silicon and/or other materials for optical and other applications

Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element.

Surface modified TSV structure and methods thereof

An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/&#xb0; C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Carrier-less silicon interposer

Growing community of inventors

Fremont, CA, United States of America

Pezhman Monadgemi