Taiwan Semiconductor Manufacturing Comp. Ltd.

Pey-Huey Chen

Chung-Cheng Chou

Subramani Kengeri

Bharath Upputuri

Ming-Zhang Kuo

Hank Cheng

Hau-Tai Shieh

Yi-Tzu Chen

Tsai-Hsin Lai

Bin-Hau Lo

Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.

Split bit line architecture circuits and methods for memory devices

The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Memory building blocks and memory design using automatic design tools

Growing community of inventors

Baoshan, China

Pey-Huey Chen