U.S. Philips Corporation

Petrus W Welles

Antonius H Nillesen

Marcellinus J Annegarn

Frits A Steenhof

Jan Van Der Meer

Johannes G Raven

Laurens Doornhein

Petrus A Nuijten

Pieter J Zijlstra

Hendrik Van Der Wal

Dionysius A Boerrigter

A field number doubling circuit has a measuring circuit (25) for determining the starting instant of a second read operation of a memory circuit (3) with respect to that of a first read operation in such a way that a display of a field number doubled television signal, even for a non-standard television signal to be doubled in field number, does not exhibit any flicker at the field frequency of the last-mentioned signal. Furthermore, the measuring circuit can determine the most favorable waiting period (B) between a write operation and a first read operation, the waiting period (A) between a vertical synchronizing pulse (V) and the start of a memory write operation, and a value for the waiting period (C) between the start of a memory read operation and the start of vertical deflection of a picture display section (13). A counter circuit (29) which can be controlled by means of the measuring circuit is provided for the controllable periods.

Field number doubling circuit for a television signal

A television synchronizing signal pattern correction circuit has a change-over switch (23) which can supply a vertical synchronizing signal (V') obtained from an input (13) or from an output (17) of a delay circuit (15). The change-over switch (23) is operated by a signal obtained from an output (31) of a simple measuring circuit (9). With the aid of two pairs of D-flipflops (35, 37; 39, 41), two exclusive-OR gates (43, 45), two AND-gates (47, 49) and a JK-flipflop (52) the measuring circuit (9) measures the mutual location of undelayed (at 11) and delayed (at 19) vertical synchronizing signals with respect to a signal (at 7) having a duty cycle of fifty percent and representing the horizontal synchronizing signals. As a result, unwanted irregularities in the selected vertical synchronizing signal can be avoided, thus making it usable for, inter alia, the synchronization of writing into a field memory.

Television synchronizing signal pattern correction circuit

In a television picture display device which can display a compressed (by 13) sub-picture of a second video signal source (29) in a main picture of a first video signal source (1), a correct mutual location of the picture information in the sub-picture with respect to the main picture is always obtained by means of a first (55) and a second (119) even-odd field identification circuit for the sub-picture and for the main picture, respectively, an interlacing circuit (71) and an interlacing-correction circuit (125), so that troublesome phenomena no longer occur in the sub-picture upon field transitions.

Television picture display device

In a television signal memory write circuit which is synchronized by horizontal and vertical synchronizing signal patterns obtained from the television signal to be entered, the mutual positions of these patterns being measured with the aid of a measuring circuit; and depending on this measurement, the vertical synchronizing signal pattern is delayed by a variable delay circuit such that in practice the patterns are prevented from coinciding, thereby preventing a change in the position of a predetermined line number in the television signal memory circuit. This renders the circuit less sensitive to interference.

Television signal memory-write circuit

In a television receiver, comprising a tuning portion (1) which operates in time-division multiplex and a first memory circuit (41) for storing sub-picture information from different transmissions obtained during a tuning cycle, a second memory circuit (57) is provided for acquiring the sub-picture information from the first memory circuit (41) in one single operation and for displaying (at 65) during a next tuning cycle a composite picture in which no change of picture content occurs.

Television receiver comprising a circuit for sequentially tuning the

In a field number conversion circuit, the mutual positions of the horizontal and vertical synchronizing signal pattern in a field of the television signal to be converted are measured by means of a measuring circuit (201) and these mutual positions are adequately transferred by means of a coupling circuit (203) to a corresponding field in the converted television signal. Reading the field memories (125, 127) used during the conversion operation is preferably effected at a clock frequency (at 53) which is not coupled to the clock frequency (at 23) used during the writing operation.

Field number conversion circuit

In a phase control loop (3, 15, 85, 87, 89, 90) for the A/D converter of a digital color television signal processing circuit an input (13) and an output (23) of a delay circuit (21) are connected to a comparator (19) to derive a control signal from the inequality of the signals at said input and output.

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Eindhoven, Netherlands

Petrus W Welles