U.S. Philips Corporation

Petrus J Van De Wiel

Leonard J Esser

Johannes A Van Gils

Leonardus A Daverveld

An information processing system comprises a sub-circuits, each performing a part of the processing of the information or data. The operation of the sub-circuits is synchronized by means of clock signals applied to clock inputs of the sub-circuits. The clock signals are derived from a system clock and are transferred to each sub-circuit via the sub-circuit or sub-circuits preceding that sub-circuit in the data processing chain. To avoid deterioration of the clock pulses while they are transferred between the sub-circuits, clock regeneration circuitry is arranged in the chain of sub-circuits. The clock regeneration circuitry is preferably integrated together with the data-processing sub-circuits.

Data processing circuit including a plurality of serially clocked

A semiconductor device including a field effect transistor, such as an insulated gate field effect transistor, which has in the direction from source zone to drain zone successive first and second channel zones with associated gate electrode parts. According to the invention, over at least 80% of the overall channel width, in a direction at right angles to the direction of source-drain current, the ratio L.sub.1 /L.sub.2 between the length L.sub.1 of the first gate electrode part and the length L.sub.2 of the second gate electrode part is variable and smaller than unity in order to improve the linearity of the field effect transistor.

Semiconductor device having a field effect transistor with improved

A semiconductor device comprising a field effect transistor of the lateral or vertical DMOST type having a source zone of the one conductivity type, an adjoining channel region of the other conductivity type, a drain zone of the one conductivity type and a weakly doped drift region located between the drain zone and the channel region. According to the invention a second gate electrode located on the side of the drain zone and separated from the first gate electrode is disposed on the insulating layer above the channel zone behind the first gate electrode located on the side of the source zone. The length L.sub.2 of the part of the second gate electrode located above the channel zone is at least equal to that of the part of the first gate electrode located above the channel zone. As a result, a high value of the mutual conductance g.sub.m as well as good linearity can be obtained. The second gate electrode is preferably made of polycrystalline silicon,which in the operating condition is depleted at least in part above the drift region.

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Eindhoven, Netherlands

Petrus J Van De Wiel