Sierra Semiconductor B.v.

Other

Vega Grieshaber Kg

Endress+hauser Gmbh+co.

Envec Mess- Und Regeltechnik Gmbh + Co.

Kavlico Corporation

Kavilco Corporation

Petrus H Seesink

Reinder L Post

Vierten M Mellert

Georg Schneider

Richard Wagner

With regard to a significant reduction in the tolerance range or margin to be taken into account in the design of a switched-capacitor circuit which is monolithically integrated by means of enhancement-mode insulated-gate field-effect transistors there is provided at least one opamp. This opamp contains a resistor which determines its quiescent current and is realized as a transistor operated in the permanently current-conducting state. An on-chip clock oscillator generates a clock signal. This oscillator is either an RC clock oscillator, whose frequency is determined by an oscillator resistor, which is realized as a transistor operated in the permanently current-conducting state, and an oscillator capacitor, or a current-controlled clock oscillator, whose frequency is determined by the quiescent current of the opamp. At least one capacitor is charged or discharged during operation by the opam via at least one switch in the form of a transistor clocked by the clock signal.

Monolithic MOS-SC circuit

This circuit arrangement has the property of an amplifier with a set or adjustable non-inverting gain and contains an opamp (3) having an a non-inverting and an inverting input (31, 32) as well as an output (33) which is also a signal output (A) of the circuit arrangement, and a current copier (8) having a current input and a current output. The noninverting input (31) is connected to a first reference potenial (P.sub.1) and the output (33) via a first resistor (1) to the inverting input (32). The input (E) of the circuit arangement is connected via a second resistor (2) to the current input of the current copier (8) the current output of which is connected to the inverting input (32). The output section of the current copier is connected to a second reference potential (P.sub.2) and its input section to the first reference potential.

Circuit arrangement with an operational amplifier

A circuit arrangement for the linearization and temperature compensation of capacitive sensor signals is provided which requires few components and wherein the compensated input signal is obtained fast. The arrangement includes: a clock generator; a reference capacitor; a measuring capacitor; a temperature-dependent voltage divider connected between an operating and a reference potential which measures the temperature of the measuring capacitor; an adjusting circuit which acts on the measuring capacitor and the reference capacitor and having a first input connected to the operating potential, a second input connected to the voltage divider, and a third input; an integrating stage connected to the measuring capacitor and the reference capacitor and having its output coupled to the third input of the adjusting circuit, the output being the output of the arrangement. The output signal is ##EQU1## where C.sub.v =(C.sub.m -C.sub.r)/C.sub.m, (C.sub.m -C.sub.r)/(C.sub.m +C.sub.r) , or (C.sub.m -C.sub.r)/C.sub.r ; C.sub.m is the capacitance of the capacitor; C.sub.r is the capacitance of the reference capacitor; U is the operating potential; a.sub.0 is a zero adjustment value; a.sub.1 is a temperature coefficient zero adjustment value; a.sub.2 is a first span adjustment value; a.sub.3 is a temperature coefficient span adjustment value; b.sub.0 is a second span adjustment value; b.sub.1 is a linearization adjustment value, and v.sub.1 is the temperature-dependent resistance ratio of the voltage divider.

Growing community of inventors

Eindhoven, Netherlands

Petrus H Seesink