Applied Micro Circuits Corporation

Qualcomm Incorporated

Quake Technologies, Inc.

Petre Popescu

Douglas Stuart McPherson

Quoc Hai Tran

Kathryn Howlett

Stanislas Wolski

Junxian Weng

Niraj Rajendra Mathur

Guy Jacque Joseph Fortier

Diana Gradinaru

Hai Tran Quoc

David Alexander Brinton Dobson

Daniel Pierre Trepanier

Stefan Szilagyi

The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Extended link monitoring channel for 10 Gb/s Ethernet

A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.

Circuit for adaptive sampling edge position control and a method therefor

The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Differential receiver circuit with electronic dispersion compensation for optical communications systems

Differential receiver circuit with electronic dispersion compensation

The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the high speed of operation, all circuits including the phase locked loop, operate as differential circuits, which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

High speed circuits for electronic dispersion compensation

Quake Transistor Logic (QTL) circuits of the embodiments of the invention are low power, high-speed circuits that can be manufactured by the same process as the lower-speed complex circuits, and are thus capable of being integrated on the same device. A number of techniques are employed to give QTL circuits their unique advantages. Lower power without loss of speed is achieved through the use of a self-biasing clock buffer to eliminate the need for tail current sources in the logic; differential signals are employed throughout to improve noise immunity with a low logic signal swing; an optional tuning circuit provides extension of the frequency response to achieve an even higher clock frequency and logic circuit bandwidth.

High speed logic circuits

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Ottawa, Canada

Petre Popescu