International Business Machines Corporation

Petra Leber

Silvia Melitta Mueller

Cedric Lichtenau

Kerstin Claudia Schelm

Steven R Carlough

Michael Klein

Reid T Copeland

Xin Guo

Stefan Payer

Jonathan D Bradbury

Klaus Michael Kroener

Nicol Hofmann

Son Trong Dao

Timothy John Slegel

Eric M Schwarz

Maarten Jakob Boersma

Daniel Lipetz

Michael Klaus Kroener

Jochen Preiss

Andreas Wagner

Razvan Peter Figuli

Dieter F Wendel

Bruce C Giamei

Jens Leenstra

Juergen Haess

James Raymond Cuffney

Christophe J Layer

Cédric Lichtenau

Wolfram M Sauer

K Michael Kroener

An instruction to perform validity testing of a source value is executed. The executing the instruction includes obtaining the source value using at least one field of the instruction and obtaining a plurality of test controls using a field of the instruction. The one or more test controls of the plurality of test controls are used to specify which digit positions of the source value are to be tested for validity and what codes are valid codes for the digit positions specified to be tested. Validity testing of at least a portion of the source value is performed based on the plurality of test controls obtained using the field of the instruction, and the performing the validity testing provides a result. The result is provided for use in further processing.

Vector test decimal instruction for validity testing

Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.

Rounding hexadecimal floating point numbers using binary incrementors

Verifying the correctness of a leading zero counter, including: generating, based on an input value comprising a plurality of digits, a first bit vector, wherein each entry of the first bit vector indicates whether a corresponding digit of the input value is equal to zero; calculating, based on the first bit vector, a leading zero count for the input value; generating a bit mask comprising a number of leading ones equal to the leading zero count; generating a second bit vector comprising a one at a same index as a first occurring zero in the bit mask; and verifying the leading zero count based on the first bit vector and one or more of the bit mask and the second bit vector.

Verifying the correctness of a leading zero counter

A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.

Repurposed hexadecimal floating point data path

An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.

Vector convert hexadecimal floating point to scaled decimal instruction

Instruction interrupt suppression for an overflow condition. An instruction is executed, and a determination is made that an overflow condition occurred. Based on a per-instruction overflow interrupt indicator being set to a defined value, interrupt processing for the overflow condition is performed, and based on the per-instruction overflow interrupt indicator being set to another defined value, the interrupt processing for the overflow condition is bypassed.

Instruction interrupt suppression of overflow exception

An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.

Hexadecimal floating point multiply and add instruction

An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

Condition code anticipator for hexadecimal floating point

An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.

Decimal scale and convert and split to hexadecimal floating point instruction

An aspect includes generating a data result and a special case indicator based on an instruction and at least one input data operand. Outputting the data result to a processor core. Outputting the first condition code to the processor core prior to outputting the data result to the processor core. Generating a second condition code based on the data result and the special case indicator. Performing a check by comparing the first condition code and the second condition code and flagging an error to the processor core upon the first condition code being different from the second condition code.

Efficient checking of a condition code anticipator for a floating point processor and/or unit

Examples of techniques for hexadecimal exponent alignment for a binary floating point unit (BFU) of a computer processor are described herein. An aspect includes receiving, by the BFU, a first operand comprising a first fraction and a first exponent, and a second operand comprising a second fraction and a second exponent. Another aspect includes, based on the first operand and the second operand being in a first floating point format, multiplying each of the first exponent and the second exponent by a factor corresponding to a number of bits in a digit in the first floating point format.

Hexadecimal exponent alignment for binary floating point unit

Digit validation check control for execution of an instruction. A process obtains an instruction to perform operation(s) using input value(s). The instruction includes a no validation indicator for controlling whether digit validation check control is enabled for execution of the instruction. The process executes the instruction, including determining, based on the no validation indicator, whether digit validation check control is enabled for execution of the instruction, and performing processing based on the determining. Based on the no validation indicator being set to a defined value, digit validation check control is enabled and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error with respect to the at least one input value.

Digit validation check control in instruction execution

Negative zero control for execution of an instruction. A process obtains an instruction to perform operation(s) using an input value. The instruction includes a negative zero control indicator indicating whether negative zero control is enabled for execution of the instruction. The process executes the instruction, the executing including performing the operation(s) using the input value to obtain a result having a sign, determining whether to control the sign of the result, the determining being based at least in part on the negative zero control indicator being set to a defined value, and performing further processing, as part the executing the instruction, based on the determining.

Negative zero control in instruction execution

A method for detecting faults in substring search operations using a processor unit including vector registers of M vector elements each. A non-limiting example of the method includes providing an M&#xd7;M matrix of comparators for characterwise comparison of the elements of a reference string and a target string. A first zero detect vector having value indicative of terminating element of the target string and a second zero detect vector having a value indicative of terminating element of the reference string are generated. A resulting bit vector is generated using comparison performed by the M&#xd7;M matrix. The resulting bit vector indicates characters of the target string that fully match the reference string and indicate characters of the target string that partially match the reference string. Fault detection in the substring search operations is performed by comparing the generated zero detect vectors with operands.

Growing community of inventors

Ehningen, Germany

Petra Leber