Semiconductor Components Industries, LLC

Petr Kadanka

Ivo Vecera

Jefferson W Hall

Christophe Basso

Antonin Rozsypal

Pavel Londak

Nicolas Cyr

A triggered sink circuit for a linear voltage regulator, such as low-dropout voltage regulator (LDO), is disclosed. The triggered sink circuit is activated only when needed to sink current from an output in response to a transient load change. The triggered sink circuit includes a large sink transistor that when activated drains current from the output of the LDO to quickly restore an output voltage back towards a regulated value, thereby improving a load transient response to the load change. The improved load transient response prevents the output transistor of the LDO from being completely deactivated to restore regulation. Accordingly, the LDO's response to a subsequent load transient can be improved.

Triggered sink circuit for a linear regulator

A low-voltage bandgap reference circuit includes a current source supplying a reference voltage rail. A first BJT has a collector coupled to the voltage rail via a resistor, a base coupled directly to the voltage rail, and an emitter coupled to ground via an emitter resistance. A second BJT has a collector coupled to the voltage rail via a resistor, a base coupled to voltage rail by a first base resistance and to ground via a second base resistance, and a collector coupled to the emitter resistance via an intermediate resistance. A third BJT has a collector driven by a current source, a base coupled to a node between the first and second base resistances, and an emitter coupled to ground. A feedback amplifier regulates the reference voltage rail to equalize collector voltages of the first and second BJTs.

Temperature-compensated low-voltage bandgap reference

According to an aspect, a low-dropout (LDO) regulator includes a pre-charge buffer, an output stage, and a noise filter connected between the pre-charge buffer and the output stage of the LDO regulator. The noise filter includes a first resistor. The LDO regulator includes a transistor configured as an input to the output stage, and a compensation circuit connected to an input of the pre-charge buffer. The compensation circuit includes a second resistor. The compensation circuit is configured to provide a compensation current that produces a first voltage drop across the second resistor, where the first voltage drop offsets a second voltage drop produced by an input current of the transistor across the first resistor.

Compensation of input current of LDO output stage

A low-voltage bandgap reference circuit includes a current source supplying a reference voltage rail. The circuit further includes a Vloop branch coupled to the reference voltage rail to obtain a Vvoltage with a negative temperature coefficient. The circuit further includes a &#x394;Vloop branch to obtain a &#x394;Vvoltage, the &#x394;Vloop branch employing a fractional Vvoltage, to provide a reduced, positive temperature coefficient. The circuit further includes a feedback amplifier that sets identical voltages from the loop branches on inputs of the amplifier A to regulate an output voltage of the circuit on the reference voltage rail at a temperature-compensated value below 1.2V.

Regulating temperature-compensated output voltage

An illustrative method embodiment includes: sensing a source-drain current provided by the output transistor; and controlling a bulk current from a body terminal of the output transistor in response to the source-drain current. The controlling includes: maintaining the bulk current at an operating value while the source-drain current is in an active range; and reducing the bulk current below the operating value when the source-drain current lies outside the active range. An illustrative circuit embodiment includes: an output transistor that supplies an output current over a range that includes an active region; and a bulk current adapter that senses the output current and responsively controls a bulk current from a body terminal of the output transistor, maintaining the bulk current at an operating value while the output current is in the active region and reducing the bulk current when the output current is outside the active region.

Bulk current regulation loop

A low dropout (LDO) voltage regulator includes a voltage regulation loop for providing a gate drive signal to an output device, the gate drive signal proportional to an output current. The voltage regulation loop includes a current bias input for receiving a bias current. The LDO voltage regulator further includes a current bias control circuit for providing the adaptive bias current at a first value that is proportional to current limit value lab and the width-to-length ratio of transistors of the transconductance amplifier when the output current less than or equal to a threshold and increases the bias current from a threshold to a current limit value. The output current varies substantially linearly over a range of output current values between the threshold and the current limit value.

Adaptive bias for low power low dropout voltage regulators

In one embodiment, a method of forming a power supply controller may include configuring the power supply controller to control a pass transistor to form an output current responsively to a control signal and independently of the value of the output voltage until the control signal is less than a deviation from a desired value of the output voltage.

Method of forming a power supply controller and structure therefor

A low dropout (LDO) regulator includes a voltage regulation loop for providing an output voltage to an output terminal, where the output voltage is proportional to a reference voltage. The voltage regulation loop includes a current bias input for receiving a bias current. The LDO regulator also includes a bias current control circuit for providing the bias current at a first value when the reference voltage is greater than a feedback voltage and at a second value higher than the first value when the reference voltage is less than the feedback voltage.

Low dropout voltage regulator including a bias control circuit

An over-power compensation circuit for use in a switched mode power supply having a current sense circuit for sensing a current flowing through a power transistor of the switched mode power supply. The over-power compensation circuit includes a peak detector, a sample-and-hold circuit, a current offset generator, and an offset resistor. The peak detector has an input for receiving an input voltage derived from the input line, and an output. The sample-and-hold circuit has an input connected to the output of the peak detector, and an output. The current offset generator has an input connected to the output of the sample-and-hold circuit, and an output for providing an offset current. The offset resistor has a first terminal connected to the output of the current offset generator, and a second terminal adapted to be connected to a current conducting electrode of the power transistor.

Over power compensation in switched mode power supplies

In one embodiment, a voltage sense circuit receives an ac input signal and forms a rectified output voltage that is representative of the ac input signal.

Voltage sense circuit and method therefor

In one embodiment, a power supply controller is configured to reset or override a soft-start reference signal responsively to the output voltage decreasing to a value that is less than a desired regulated value of the output voltage.

Power supply soft start controller with no output voltage undershoot when transitioning from skip cycle mode to normal mode

In one embodiment, a reference generator forms a reference signal that may have temperature and process variations. A comparator that has similar variations is used to detect a signal using the reference.

Accurate timing generator and method therefor

A variable-frequency oscillator () is formed to change an internal delay of the oscillator inversely proportional to changes in the frequency of the oscillator.

Method of forming a variable frequency oscillator and structure therefor

A circuit ( ) having multiple poles within an active frequency range employs a movable zero ( ) to maintain stability in the circuit ( ) under variable load conditions. A pole ( ) created by a frequency compensation element ( ) maintains a fixed frequency within the active frequency range of the circuit ( ). In addition, a variable load impedance ( ) coupled to the circuit ( ) generates a load pole ( ) within the active frequency range of the circuit ( ) that changes frequency over time. As the load pole ( ) changes frequency, the frequency of the movable zero ( ) is adjusted to achieve an enhanced stability condition within the circuit ( ). In one embodiment, the frequency of the movable zero ( ) tracks the frequency of the load pole ( ) as the load impedance ( ) changes.

Method and apparatus for maintaining stability in a circuit under variable load conditions

A band gap reference ( ) provides low noise operation utilizing capacitor ( ) to produce a low pass filter operating with high impedance node ( ). Increased speed is realized using feedback signals at nodes ( ) and ( ) to control differential transistor pair ( ). A first current feedback stage using transistors ( and ) and a second current feedback stage using transistors ( ) is used to control current mirror stages which set the charge and discharge current at node ( ). A first current mirror stage using transistors ( ) comprise the current sink used to discharge capacitor ( ) at node ( ) and a second current mirror stage using transistors ( ) comprise the current source used to charge capacitor ( ) at node ( ).

Growing community of inventors

Valasska Bystrice, Czechia

Petr Kadanka