Motorola Corporation

Freescale Semiconductor,inc.

Peter Zurcher

Melvy Freeland Miller, Iii

Robert E Jones

Sriram Kalpat

Thomas P Remmel

Ajay Jain

Bo Jiang

Peir-Yung Chu

Matthias Passlack

Jonathan K Abrokwah

Papu D Maniar

Bruce E White

Philippe Renaud

Bruno Chaudret

Karthik Rajagopalan

Catherine Amiens

Marie Claire Fromen

Marie-Jose Casanove

Roland Stumpf

Rashaunda Monique Henderson

Haiping Zhou

Sergio Palma Pacheco

Richard J Hill

Peir Chu

Xu Li

David A Moran

Iain G Thayne

Frederic Dumestre

Melvy F Miller

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form a top electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Semiconductor device comprising passive components

A semiconductor fabrication process includes forming a gate dielectric layer () overlying a substrate () that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure () that has a substantially vertical sidewall (), e.g., a slope of approximately 45&#xb0; to 90&#xb0;. A metal contact structure () is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap () between the two. The wafer () is heat treated, which causes migration of at least one of the metal elements to form an alloy region () in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer () is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

III-V MOSFET fabrication and device

A method is provided for constructing a microelectronic assembly. A semiconductor substrate having a MEMS device formed on a first portion thereof, a semiconductor device formed on a second portion thereof, and a build up layer having a first portion formed over the MEMS device and a second portion formed over the semiconductor device is provided. The first portion of the build up layer over the MEMS device is removed. A release body is formed adjacent to the MEMS device. A structural material is formed over the release body. An opening is formed in the structural material to expose the release body. The release body is removed through the opening to form a cavity between the MEMS device and the structural material. The opening in the structural material is sealed with a sealing material.

Method for forming and sealing a cavity for an integrated MEMS device

A magnetic nanoparticle (), a magnetic nanomaterial (), assembly (), and a method for synthsising a magnetic nanoparticle, relating to thermodynamically stable and air stable ferromagnetic nanoparticles of adjustable aspect ratio made upon decomposition of organometallic precursors in solution in the presence of a reaction gas and a mixture of organic ligands. The magnetic nanomaterial comprises magnetic nanoparticles of homogeneous size, shape, and magnetic orientation that comprises a magnetic core () ferromagnetic at room temperature and/or operating temperatures, and a non-magnetic matrix () encapsulating the magnetic core. This magnetic nanomaterial could be used in high frequency integrated circuit applications, such as used in wireless portable electronic devices, to enchance magnetic field confinement and improve passive component performance at MHz and GHz frequency in a variety of passive and active devices, such as transformers, on-chip signal isolation, inductors, and the like.

Magnetic nanomaterials and synthesis method

A method of making a semiconductor device includes the steps of: providing a semiconductor substrate () having a patterned interconnect layer () formed thereon; depositing a first dielectric material () over the interconnect layer; depositing a first electrode material () over the first dielectric material; depositing a second dielectric material () over the first electrode material; depositing a second electrode material () over the second dielectric material; patterning the second electrode material to form a top electrode () of a first capacitor (); and patterning the first electrode material to form atop electrode () of a second capacitor (), to form an electrode () of the first capacitor, and to define a resistor ().

Method of making a semiconductor device, and semiconductor device made thereby

An electromechanical resonator includes a substrate (), an anchor () coupled to the substrate, a beam () coupled to the anchor and suspended over the substrate, and a drive electrode () coupled to the substrate and separated from the beam by a gap (). The beam has a first surface (), a second surface (), and a third surface (). The first surface defines a width and a height, the second surface defines the height and a length, and the third surface defines the length and the width. The width, height, and length are substantially mutually perpendicular, and the beam resonates substantially only in compression mode and substantially only along an axis defined by the length.

Electromechanical resonator and method of operating same

A semiconductor device and a method of making a semiconductor device. A damascene metal layer ( ) is formed in an insulating dielectric layer ( ), which is in direct electrical communication with a substrate ( ). A layer of a passive element, such as first capacitor electrode layer ( ) is disposed on metal layer ( ) and preferably is offset relative to metal layer ( ) to allow a direct electrical interconnect through a via ( ) to metal layer ( ). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor ( ) and optionally a second resistor ( ). In yet another embodiment, metal layer ( ) is a damascene copper layer.

Semiconductor device having passive elements and method of making same

Method of making semiconductor device having passive elements including forming capacitor electrode and resistor from same layer of material

Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.

Method for forming a semiconductor device

A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Method for making a ferroelectric device having a tantalum nitride

A method and apparatus for simulating the design of a ferroelectric circuit uses a processor (501). The processor (501) executes a simulator (540) from memory (538) to exercise a ferroelectric model (544). The ferroelectric model (544) keeps track of turning points or extrema points (FIGS. 11-17) in a history data file (542). This history data in file (542) is then used with eqs. 3-11 herein to curve model between voltage/charge history points from the file (542) and a current operating voltage/charge point of the ferroelectric device. This curve modeling effectively and efficiently determines the charge stored in a ferroelectric capacitor (FIGS. 7 or 8) as voltage across the ferroelectric capacitor is varied over time and temperature. History data points are selectively removed from the data file (542) to maintain and enable time-efficient determination of charge (Q) in the ferroelectric device over time.

Ferroelectric simulator, ferroelectric method of manufacture, and method

A method for forming an embedded DRAM structure along with tungsten plugged MOS transistor devices begins by forming capacitor tungsten plugs (46) and bit-line tungsten plugs (44). A bottom capacitor electrode (48b) is formed to protect the tungsten plug (46). Simultaneously, an optionally-removable barrier region (48a) is formed to protect the plug (44). A capacitor dielectric (52) is deposited and oxygen annealed to form a ferroelectric capacitor material. The barrier (48a) and the lower electrode (48b) protect all of the tungsten plugs (46 and 44) from being adversely oxidized by the oxygen anneal. A top electrode (54 and 56) of the ferroelectric capacitor is then deposited, lithographically patterned, and etched. The lithographic patterning and etching of the top electrode may also be further utilized to remove the barrier region (48a).

Plug protection process for use in the manufacture of embedded dynamic

Method for making a ferroelectric device

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Phoenix, AZ, United States of America

Peter Zurcher