Digital Imaging Systems Gmbh

Power Survey Company

Other

Sri International

Dialog Semiconductor Gmbh

Peter Zalud

Nathaniel Joseph McCaffrey

Peter Alan Levine

David Kalokitis

Christos Alkiviadis Polyzois

Gary Hughes

David Christopher Berends

Robert W Evans

Jonathan Lloyd Schepps

John Thomas Kalinowski

Frederick John Vannozzi

Frank Bowen Lang

Min-Long Lin

Scott Thomas Smith

A ROIC can perform systolic processing of light detectors. The ROIC performs the systolic processing of the light detectors to capture at least i) when, in time units, an initial photon of its reflected light pulse is captured by each of the light detectors in the array, ii) where geographically in terms of column and row address of the light detector capturing its photon is located in the array, iii) scan out data captured by the light detectors on the when in time units, and the where geographically that the photon was captured in a given light detector in the array, and then iv) analyze the data on the when and the where with an algorithm to know exactly when exactly, in terms of time units, the photon was captured relative to the input from the clock circuit in order to determine an objects characteristics.

Systolic processor system for a light ranging system

A new method of reading an imager is achieved. The method comprises providing an imager array comprising n rows and m columns where a pair of rows can be read during a single row access time. A first image field is completed by sequentially reading and storing pixel values of pairs of adjacent rows of the imager array. The reading begins at a first row, and the reading stops when less than three rows are unread. Thereafter pixel values of the next row are read and not stored. Thereafter pixel values of the first row of the imager array are read and not stored. A second image field is completed by sequentially reading and storing pixel values of pairs of adjacent rows. The reading begins at the second row, the reading stops when less than two rows are unread.

Simultaneous readout of CMOS APS imagers

A method for sensing an electric field includes processing digitized electric field signals, e.g., from an electric field sensing probe. The processing may include performing a Fast Fourier Transform of the digitized electric field signals to provide an indication of the magnitude of the electric field, and may include processing the digitized electric field signals at a rate that is related to the speed at which a movable sensing probe is moving. The method may include performing unweighted and/or weighted averaging in relation to processing electric field data, setting a comparison threshold, providing a human perceivable indication, or a combination of the foregoing.

Method for sensing an electric field

A sensor for sensing an electric field includes a movable sensor probe including one or more pair, typically three pair, of electrically conductive electrodes, and may include one or more pair of selectively switchable auxiliary electrodes. The probe is movable and may be mounted on a vehicle or trailer. A processor may process electric field signals from the probe for providing a human perceivable indication of the electric field. The processor may perform a Fast Fourier Transform of the electric field signals to produce an indication of the magnitude of the electric field, and may perform unweighted and/or weighted averaging in relation to processing electric field data, setting a comparison threshold, providing a human perceivable indication, or a combination of the foregoing. A speed at which the sensor probe is moving may be utilized in processing the data.

Apparatus and method for detecting an electric field

There is shown an single chip CMOS device for capturing a video image. The device includes an APS imager containing an array of pixels for providing a signal representing a scene, a row of extended dynamic range sample and hold circuits for receiving a signal from the array of pixels and a row of linear sample and hold circuits for receiving another signal for said array of pixels. Also included is an image processor for determining a controllable function and for processing a plurality of signals received from the extended dynamic range sample and hold circuits and the linear sample and hold circuits according to said controllable function to form a processed video signal. Further included is a memory for storing the controllable function and the processed video signal.

Fully integrated solid state imager and camera display

An apparatus is described for reducing coherent signal interference between at least two bit streams framed with a common clock signal. The apparatus includes an internal clock signal generated from the common clock signal and a Manchester encoder for encoding the internal clock signal with a unique signature. Also included is a logic AND-gate for combining one bit stream of the two bit streams with the encoded clock signal to produce an encoded output signal. When the encoded output signal is combined with another of the two bit streams during transmission, individual bits of the combined bit streams are identifiable at a receiving end. The receiving end decodes the combined bit streams and properly discriminates between ONEs and ZEROs.

Encoding/decoding system for coherent signal interference reduction

Growing community of inventors

New Hope, PA, United States of America

Peter Zalud