Intel Corporation

Peter Yiannacouras

Nagabhushan Chitlur

Josh Triplett

Kalyan Kondapally

Radhakrishna Sripada

A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.

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Toronto, Canada

Peter Yiannacouras