Altera Corporation

Peter Yiannacouras

John Stuart Freeman

Deshanand Pratap Singh

Tomasz Czajkowski

A method for designing a system on a target device includes describing the system in a high-level synthesis language where the system includes a configurable clock to drive the system at a specified clock frequency. A hardware description language (HDL) of the system is generated from the high-level synthesis language. An initial compilation of the HDL of the system is performed in response to the specified clock frequency. Timing analysis is performed on the system after the initial compilation of the HDL to determine a maximum frequency which the system can be driven. The configurable clock is programmed to drive the system at the maximum frequency.

Method and apparatus for satisfying operating conditions in a system design using an electronic design automation tool

Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.

Guided memory buffer allocation

Systems and methods for limiting resource usage of a kernel of an integrated circuit are provided. For example, in one embodiment a method for limiting a number of workgroups that may simultaneously access a kernel of an integrated circuit (IC) includes determining a threshold number of workgroups that may access the kernel simultaneously. A thread of execution is received. The thread of execution is allowed to access the kernel when the threshold number of workgroups would not be exceeded by the thread of execution accessing the kernel.

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Etobicoke, Canada

Peter Yiannacouras