Aplus Flash Technology, Inc.

Aplus Integrated Circuits, Inc.

Other

Salesforce Com, Inc.

Ameriphone, Inc.

American Phone Products, Inc.

Twilio Inc.

Plantronics, Inc.

Aplvs Flash Technology, Inc.

Abedneja Assetts Ag L.l.c.

Abedneja Assets Ag L.l.c.

Peter Wung Lee

Fu-Chang Hsu

Hsing-Ya Tsao

Han-Rei Ma

Koucheng Wu

George F Cheung

Vei-Han Chan

Hung-Sheng Chen

Vinod Mehra

Rob Woollen

Mervyn Wong

Jeffrey Gordon Lawson

Kesheng Wang

Rob Brazier

Manav Khurana

Mike Hsinyih Chen

Matthew Francis Davidchuk

William Gradin

Rasmus Mencke

Amy Palke

Qiu Ma

Leonid Zemskov

Margaret Law

Tam Huu Tran

Jamal M Ayache

Nancy M Lee

Fu-Change Hsu

Kwok-Yeung Alexander Lai

Wen-Tan Fan

Kenneth W Schossow

Phuong Le Pham

Joe T Yee

A system and method for facilitating contextual communications that includes creating a contextual resource that is initially associated with at least at first communication session; receiving an incoming communication request and establishing a second communication session; associating the second communication session with the contextual resource; setting contextual information of the contextual resource; performing at least one contextual communication action.

System and method for contextual communication

A charging and drying station includes a main casing having a receiving cavity, a drying arrangement and a charger accommodation arrangement. The charger accommodation arrangement includes a utility platform securely mounted on the main casing. The utility platform has a through charger accommodating slot, wherein the charger accommodating slot is shaped and sized to fittedly accommodate at least the charging terminal of the hearing aid charger when the hearing aid charger is detachably accommodated in the receiving cavity, so that the hearing aid device is capable of being disposed on the utility platform for being simultaneously recharged and dried by the hearing aid charger and the drying arrangement respectively.

Charging and drying station for hearing aid device

A diaper includes a diaper body and a wet diaper monitoring device, which includes a disposable pouch and a monitoring device. The monitoring device includes a monitoring casing, a first sensor electrode, a second sensor electrode, a sensing circuitry and an indicator. The first sensor electrode and the second sensor electrode are provided on an inner surface of and received in the monitoring casing, and form a single planar capacitor when the diaper body is dry. When the diaper body becomes wet, a capacitance between the first sensor electrode and the second sensor electrode increases substantially so as to transform the single planar capacitor of the first sensor electrode and the second sensor electrode into two much larger series connected capacitors.

Diaper with wet diaper monitoring device

A universal charging and drying station includes a main unit and a hearing aid charger. The main unit includes a main casing, a lid, a hearing aid dryer, and a control circuitry. The hearing aid charging includes at least one interchangeable adapter unit, which includes a receptacle connector, a charging adapter and a connecting module. The connecting module has an adapter terminal electrically connecting to the hearing aid, and a plurality of connecting members detachably connected to the receptacle connector of the main casing. The interchangeable adapter unit may be operated between a charging mode and an interchangeable mode, wherein in the charging mode, the connecting module is electrically connected to the receptacle connector through the connecting members for charging the hearing aid, wherein in the interchangeable mode, the connecting module is detached from the receptacle connector for interchange of the interchangeable adapter unit.

Universal charging and drying station for hearing aid

The disclosure provides methods and compositions useful for identifying a subject's predisposition to a gastrointestinal disease or disorder.

Method to predict or diagnose a gastrointestinal disorder or disease

Wireless speaker

Systems, apparatus, and methods for implementing enterprise level social and business information networking are provided. Users can receive relevant information about a database system and its users at an appropriate time. Users can then use this relevant information to reduce errors and limit redundant efforts. For example, an update of a record in the database can be identified, and a story created automatically about the update and sent to the users that are following the record. Which updates have stories created and which stories are to be sent to which users can be configured. Other events besides updating of records can also be tracked. For example, actions of a user that result in an event can be tracked, where such tracking can also be configurable. Subscriptions to follow an object can be automatic, and access checks can be used to ensure that unauthorized users do not see certain data.

Customizing enterprise level business information networking

A hierarchical-GBL/LBL NAND array with a plurality of LG and MG groups in either orthogonal BL/CSL scheme or parallel BL/SL scheme including a plurality of block-decoders with a shared self-timed delay control circuit and a plurality of fully-shielding dynamic CACHE registers made of 2 local broken metal lines within the array and DRAM-like SA is provided. Each DCR capacitor is flexibly expandable by connecting multiple Cs made by the local broken metal lines of the LGs to form a Cof a larger MG. Based on the NAND array, multiple randomly selected WLs in multiple random blocks within multiple random LGs within one MG can be selected on basis of one WL per block per LG for performing an ABL pipeline and concurrent SLC program without verification, and on basis of one WL per block per MG for performing an ABL-like or HBL pipeline and concurrent SLC read.

Self-timed SLC NAND pipeline and concurrent program without verification

A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common V-based Vt-compensation and Vcompensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without Vpunch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.

NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations

This invention discloses 2D or 3D NAND flash array in two-level BL-hierarchical structure with flexible multi-page or random-page-based concurrent, mixed SLC and MLC Read, Program or Program-Verify operations including bit-flipping for each program state or any combinations of above operations. Tracking techniques of self-timed control and algorithm of programming, read and local-bit line (LBL) voltage generations are proposed for enhancing automatic controls over charging and discharging of a plurality of WLs and LBLs in one or more randomly selected Blocks in one or more Segments of one or more Groups in a NAND plane for m-page concurrent operations using Vdd/Vss to Vinh/Vss Program page data conversion, multiple pseudo CACHEs based on LBL capacitors for storing raw SLC and MSB/LSB loaded page data, writing back or reading from Sense-Amplifier, Program/Read Buffer, real CHCHE, and multiple pseudo CACHEs with M-fold reduction in latency and power consumption.

2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify

A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.

Partial/full array/block erase for 2D/3D hierarchical NAND

Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vsupply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.

NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations

This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

Multi-task concurrent/pipeline NAND operations on all planes

Growing community of inventors

Saratoga, CA, United States of America

Peter Wung Lee