Synopsys, Inc.

International Business Machines Corporation

Peter Wohl

John A Waicukauski

Thomas W Williams

Frederic J Neuveux

Rohit Kapur

Emil I Gizdarski

Andrea Costa

Wolfgang Meyer

Mark Alan Erle

Timothy N Ayres

Mark Eric Pedersen

Yasunari Kanzawa

Matthew Christopher Graf

Demosthenes Anastasakis

David P Appenzeller

Khader Abdel-Hafez

Michael Dylan Dsouza

Sanjay Ramnath

Tony Taylor

Gregory A Maston

Timothy G Hunkler

Techniques for performing efficient automatic test-pattern generation (ATPG) are disclosed. ATPG may be performed by ATPG workers whose fault states are synchronized by an ATPG manager. In some embodiments, test-pattern generation by a ATPG worker may be performed multiple times with minimal idle time between generation and fault simulation intervals. Synchronization schemes may be synchronous or asynchronous. In asynchronous schemes, an ATPG worker may determine staleness of its fault state. If the fault state is stale, the ATPG worker may poll the ATPG manager to update the fault state to the current fault state of the ATPG manager which includes information on faults detected (including duplicate faults) by other ATPG workers. In synchronous schemes, fault states may be synchronized without polling by the ATPG worker. The synchronization of fault states via communication between manager and workers may reduce duplication and idle time, hence improving the time efficiency of ATPG workers.

Distributed test pattern generation and synchronization

A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.

Multi-cycle test generation and source-based simulation

A system and method are provided for testing logic using a logic built in self-test (LBIST) system, and in particular where the LBIST system tolerates unknown inputs (Xs) to the logic cells forming an XLBIST system. The system allows for providing multiple test system clocks from the LBIST system to the logic during a system clock capture cycle of a system clock during testing of the logic, wherein the system clock is separate from the multiple test system clocks of the LBIST system. Further, timing of an application of clock cycles of the multiple test system clocks of the LBIST system is controlled and provided to the logic during the system clock capture cycle.

Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)

A circuit is described that can include: a first register to store a first value that specifies a first subset of a set of scan chains, wherein the first subset of the set of scan chains includes scan cells that are desired to be masked; a second register to store a second value that specifies, in each shift cycle, a second subset of the set of scan chains, wherein the second subset of the set of scan chains includes scan cells that are desired to be masked; and a masking circuit to mask, in each shift cycle, scan cells in a third subset of the set of scan chains that is an intersection of the first subset of the set of scan chains and the second subset of the set of scan chains.

Per-shift X-tolerant logic built-in self-test

A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where:

Reducing X-masking effect for linear time compactors

A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.

Increasing compression by reducing padding patterns

Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Diagnosis and debug with truncated simulation

Diagnosis and debug using truncated simulation

A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.

Two-level compression through selective reseeding

An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed.

Increasing PRPG-based compression by delayed justification

Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.

Fully X-tolerant, very high scan compression scan test systems and techniques

A method to increase automatic test pattern generation (ATPG) effectiveness and compression identifies instances of 'majority gates' and modifies test generation to exploit their behavior so that fewer care bit are needed. This method can increase test coverage and reduce CPU time as previously aborted faults are now tested. The majority gate enhanced ATPG requires no hardware support and can be applied to any ATPG system.

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Williston, VT, United States of America

Peter Wohl