Infineon Technologies Ag

Newlogic Technologies Gmbh

Wipro Limited

Peter Widerin

Dieter Metzner

Paul Wallner

Thomas Rickes

David Astrom

Thomas Stoll

A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Bus driver circuit with improved transition speed

An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Over-current detection for bus line drivers

An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.

Shutdown protection for bus line drivers

A signal downconverter having a pair of passive double sideband mixers for receiving quadrature RF signals and mixing the same with local oscillator driving signals to provide mixed differential signals. The mixed differential signals are fed to a differential difference feedback amplifier high frequency ripples are eliminated and finally providing a down converted output signal.

Signal downconverter

The invention relates to a dual band frequency synthesizer for generating either a first output frequency for a second output frequency f, where f=2 f, comprising an oscillator circuit for generating at its output a frequency f=(f+f)/2, a divide by three (3) circuit, coupled to the output of the oscillator circuit, for generating at its output an offset frequency f=f/3, and a double quadrature mixer circuit, coupled to the output of the oscillator circuit and to the output of the divide by three circuit, for generating either the first output frequency f=f+for the second output the frequency f=f&#x2212;f.

Dual band frequency synthesizer

The quadrature divider comprises a plurality of flip-flops, including at least a first flip flop and an endmost flip-flop, interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes differential inputs, differential outputs and differential clock inputs, the outputs of one flip-flop are connected to the corresponding inputs of a subsequent flip-flop, the outputs of the endmost flip-flop are connected inversely to the inputs of the first flip-flop, wherein the flip-flops are clocked at their clock inputs with differential clock signals in a consecutive manner which, for each flip-flop and depending on the dividing ratio, are individually selected from quadrature clock input signals.

Growing community of inventors

Hoerbranz, Austria

Peter Widerin