Ncr Corporation

Intel Corporation

Peter Washington

Richard R Barton

Larry C James

John H Waters

Edward A McDonald

Vernon Keith Boland

Arthur F Cochcroft, Jr

A multi-processor computer system that includes at least one &ldquo;regular&rdquo; processor and one &ldquo;enhanced mode&rdquo; processor. The enhanced mode processor is preferably not turned over to the regular processor, but is initialized to look like an internal or external device, such as a disk drive or the like. In a preferred embodiment, fast access memory that is outside the addressable range of the regular processor is coupled to the enhanced mode processor and accessed through a RAM-disk device driver. In this manner, the amount of fast access memory available to the regular processor is increased.

Accessing beyond memory address range of commodity operating system using enhanced operating system adjunct processor interfaced to appear as RAM disk

Memory controller logic for concurrently obtaining memory access locality information by cycle type for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. The monitoring logic further includes a programmable cycle control register and comparison logic to condition the page access counters for specific memory cycle types, such as coherency cycles, reads, writes, copyback cache cycles, etc. Whenever the processing node generates a transaction requiring access to a memory address within system memory which matches the cycle type specified in the cycle control register, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns by cycle type is created which can be used to optimize memory and process assignments in the computer system.

Method and apparatus for monitoring bus transactions based on cycle type

A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

Method and apparatus for determining memory page access information in a

An apparatus and method for controlling the location of pages in a system having multiple processors and multiple main memory. Local and remote accesses to main memory are monitored and when remote accesses exceed local accesses in a predefined period, steps to alleviate the volume of remote accesses are undertaken. The steps may result in the relocation of a memory page, replication of a memory page (for read only pages) and relocation of a process.

Memory page location control for multiple memory-multiple processor

A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.

Method and apparatus for enabling physical memory larger than

A method and computer system are disclosed for executing family generic, processor specific files. In accordance with one embodiment of the present invention, there is provided a method of executing a file on a computer system. The method includes the computer implemented steps of determining the processor type of a processor; storing a processor type identifier that represents the determined processor type of the processor; executing a first plurality of instructions that includes instructions exclusively from a common set of instructions that are common to a plurality of processor types; executing a second plurality of instructions that is optimized for a first processor type, if the processor type identifier indicates that the processor is of the first processor type; and executing a third plurality of instructions that includes instructions exclusively from the common set of instructions, if the processor type identifier indicates the processor is of a type different than the first processor type.

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Little Mountain, SC, United States of America

Peter Washington