International Business Machines Corporation

Peter Verwegen

Steven Frederick Oakland

David E Lackey

Niels Fricke

Christoph W Wandel

Karsten Muuss

According to one embodiment of the present invention, a method for optimizing an integrated circuit design is provided. The method may include identifying one or more nets crossing a boundary between a parent block, having parent logic, and a child block, having child logic. The method may include inserting interior buffers on the nets inside of the child block and exterior buffers on the nets outside of the child block and inside of the parent block, wherein the interior buffers and the exterior buffers define a buffer pair for each of the nets. The method may further include determining a first placement for the parent logic and a second placement for the child logic, such that the buffers of the buffer pair for each net are placed substantially near to one another. The method may further include determining pin locations for the child block based on the second placement.

Optimization of integrated circuit physical design

An edge triggered system is provided having a data and scan input includes a latch device having a clock input and an AND gate, coupled to the latch device, structured and arranged to receive a first clock signal and an inverted clock signal to generate a clock to the clock input. A process for operating an edge triggered system having a data and scan input includes forwarding a first clock signal to an input of an AND gate. The method includes inverting a second clock signal forwarded to another input of the AND gate and generating a clock input for a latch device from the AND gate.

Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility

Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility

A binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable that comprises an edge triggered master. The binary latch comprises an edge triggered master flip-flop (), with a clock input connected to the system clock (SYS_CLK), with a data input (DI) and with an output (DO), a level sensitive scan design (LSSD) slave latch (), connected to the output (DO) of the master flip-flop (), a NAND gate () with a first input () connected to the system clock (SYS_CLK), a second input () connected to a test input (TEST) and with an output () connected to the LSSD slave latch clock input (LSSD_clk).

Edge-triggered master + LSSD slave binary latch

A zero volt/zero current fuse arrangement included of two coupled latches is provided, especially for use with interconnect layers made of copper, which prevents the dendritic growth of copper and thus reduces the possibility of 'regrowing' the fuse after it has been blown.

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Rottenburg, Germany

Peter Verwegen