Catena Holding B.v.

Nxp B.v.

Peter Van Der Cammen

Erik Olieman

Mark Stoopman

A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals. The latches receive two delayed input signals provided by the delay circuits based upon the feedback signals.

Negative-feedback four-phase generator with twenty-five percent duty cycle output

The disclosure relates to a square wave RC oscillator circuit, example embodiments of which include an oscillator circuit for generating an output square wave signal (OUT) having first and second voltage output levels (L, H), the oscillator circuit comprising: a comparator having an output and first and second inputs; a switching circuit configured to provide an oscillatory waveform at the first input of the comparator; and a feedback circuit arranged to sample the first input of the comparator each time the output square wave signal (OUT) switches between the first and second voltage output levels (L, H) and to compare this sampled voltage with first and second reference voltages (V, V) to adjust a voltage provided to the second input of the comparator.

RC oscillator

The method determines an input phase differential (&#x394;&#x3c6;) between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R) and the second impedance (R) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential (&#x394;&#x3c6;) is determined when the differential mode output voltage (Vdm) is zero.

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Delft, Netherlands

Peter Van Der Cammen