St-ericsson Sa

Nxp B.v.

Oct Circuit Technologies International Limited

Peter Van Den Hamer

Andrei Radulescu

Ewa Hekstra-Nowacka

Gerrit Willem Den Besten

Artur Tadeusz Burchard

Maarten Peter Bodlaender

Cornelis Hermanus Van Berkel

Hendrik Dirk Lodewijk Hollmann

Dennis Koutsoures

Bipin Balakrishnan

Bernardus Adrianus Cornelis Van Vlimmeren

Atul Pratap Chauhan

Atul P S Chauhan

A data tag containing self-descriptive data, a method for reading such a data tag and a system for interpreting such a data tag are disclosed. Characterizing information about a first data element stored in a memory of the data tag is stored in a first header preceding a first data element. In addition, characterizing information about a second data element stored in the memory of the data tag is stored in a second header preceding a second data element. The application of a multitude of descriptive headers, each characterizing a data element stored in the data tag memory, facilitates flexible data storage on such devices. Furthermore, it also facilitates data compression due to the fact that field lengths can be characterized as well, thus excluding the presence of redundant bits in the data stored in the memory.

Self-descriptive data tag

Link startup systems, methods and devices associated with interconnects are described. Asymmetric lane connections are supported by, for example, independent renumbering of the connected lanes after an initial discovery process. Low-power, hibernating states of devices are supported by, for example, initialing alternating between transmission of startup and wakeup sequences over the interconnect between devices.

Methods and systems for reliable link startup

Disclosed are methods, and control devices () having programmable processors configured to implement methods, of communicating with a network () having an initially unknown topology and a plurality of unknown devices. The methods use set and get configuration commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

Automatic network mapping from a host control device

A method of communicating between a transmitter and a receiver based on frames is provided. An error detection code is added to each frame to be transmitted by the transmitter. The frames to be transmitted by the transmitter are transmitted and the transmitted frames are received by the receiver. An error detection code is re-computed based on the received frames by the receiver. At least one frame which has been correctly received based on a comparison of the error detection code of each frame with the re-computed error detection code of each received frame is acknowledged. An error indication frame is sent by the receiver when an error is detected based on the comparison result. If a retransmission condition is detected by the transmitter by receiving an error indication frame from the receiver or if no acknowledgement frame was received by the transmitter from the receiver in a predetermined time interval, the currently transmitted frame is aborted and the transmitter inserts a trailer. As a further possibility instead of inserting a trailer, the start of re-transmission can be indicated by using a retransmission indicator.

Method of communication, in particular with capability of frame abortion or retransmission indication, between a transmitter and a receiver based on frames and corresponding communication node

A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state. The data processing system has at least one detecting facility that detects whether the other modules have notified that they are in the second operational state and the modules each have an initialization facility for resetting the time-slot counter when the module is in the second operational state and each of the other modules has notified that it is in the second operational state.

System and method for synchronising a data processing network

A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

Memory controller and method for coupling a network and a memory

A bus station circuit () operates in an electronic system with a bus (). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

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Waalre, Netherlands

Peter Van Den Hamer