Arm Limited

Peter Uttley

Seow Chuan Lim

Richard Andrew Paterson

Robert John Harrison

Kar Lik Kasim Wong

Martin Peter Brown

Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal, the slave counter circuitry having associated fault detection circuitry; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry, the master counter circuitry being configured to provide via the synchronisation connection: initialisation data at an initialisation operation; and fault detection data at a fault detection operation; the initialisation data and subsequent fault detection data each representing respective indications of a state of the master count signal; the slave counter circuitry being configured, during an initialisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the initialisation data provided by the master counter circuitry; and the fault detection circuitry associated with the slave counter circuitry being configured, during a fault detection operation for that slave counter circuitry, to detect whether a counting operation of that slave counter circuitry generates a slave count signal which is within a threshold count difference of a fault detection count value dependent upon the fault detection data provided by the master counter circuitry.

Counter circuitry and methods including a master counter providing initialization data and fault detection data and wherein a threshold count difference of a fault detection count is dependent upon the fault detection data

Clock signal control circuitry comprises a clock selector to output a current clock signal selected from two or more candidate clock signals and to execute a clock signal change operation to select a different one of the two or more candidate clock signals for output as the current clock signal; a counter to generate a count value by counting clock pulses of the current clock signal multiplied by a scaling value; and control logic to execute a scaling value change operation to change the scaling value in response to initiation of a clock signal change operation; in which the clock selector and the control logic are configured to cooperate to inhibit the output of the current clock signal during a scaling value change operation.

Clock signal control

A data processing apparatusincludes processing circuitryperforming processing operations which move the processing circuitrybetween logical states. Monitoring circuitrymonitors logical state variables of the processing circuitry and these are supplied to prediction circuitrywhich detects predetermined patterns within the logical states which are indicative (previously correlated with) of a future potential temporary insufficiency in the supply power to the processing circuitry. When such a pattern is detected, then power control circuitryserves to trigger a mitigation response to counteract the future potential temporary insufficiency in power supply, such as temporarily reducing the clock frequency and/or boosting the supply voltage.

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Nottingham, United Kingdom

Peter Uttley