Infineon Technologies Ag

Infineon Technologies North America Corp.

Peter Thwaite

Jochen C Beintner

Wolfgang Hokenmaier

Martin Versen

Bernhard R Liegl

Enio L Carpi

A method and apparatus for reducing power consumption of a memory device. The method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective wordlines and, during the precharge operation, driving the identified defective word lines to the precharge voltage.

Redundant wordline deactivation scheme

A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines. A plurality of sense amplifiers are provided, each of which is connected to at least a first pair of bitlines to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersection of a single wordline with said first pair of bitlines, respectively. As a result, each cell of a twin storage cell can be accessed with a single wordline.

Sense amplifier organization for twin cell memory devices

A self-refresh module includes an oscillator configured to provide a first signal having a first frequency, a trimming divider configured to trim the first signal to provide a second signal having a second frequency, and a temperature sensor configured to sense a temperature of the memory device and provide a temperature signal. The self-refresh module includes a temperature look-up table configured to receive the temperature signal and provide a third signal based on the temperature signal, and a temperature divider configured to provide a self-refresh pulse signal based on the second signal and the third signal.

Temperature dependent self-refresh module for a memory device

A memory device () includes an array () of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder () is coupled to rows of memory cells while a column decoder () is coupled to columns of the memory cells. A refresh controller () is adapted to generate memory cell addresses for array () during a refresh sequence. In a preferred embodiment of the present invention, the refresh controller ensures that no shared sense amplifiers () are activated during consecutive refresh cycles, allowing a portion or all of the time required for precharging the bitlines to be saved. In a preferred embodiment, consecutive refresh cycles can be located closer together in time because a second refresh cycle may be initiated prior to the completion of a first refresh cycle.

System and method for refreshing a dynamic memory device

There is provided a method for aligning a semiconductor wafer and a mask. A semiconductor wafer is provided having an alignment mark formed thereon. A mask is provided having a pattern formed thereon. The mask is illuminated so as to create a bright spot thereon by a 0_&pgr; phase conflict. The alignment mark is aligned with the bright spot, so as to align the semiconductor wafer with the mask. Preferably, the method includes the step of creating the alignment mark on the semiconductor wafer in a form of a frame. Moreover, preferably, the creating step includes the step of creating the frame to minimize an impact of film stack variations.

Alignment system and method using bright spot and box structure

An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

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Peter Thwaite