Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Peter Theodore Panousis

Robert Leonard Pritchett

Dennis J Lynes

Friedolf Michael Smits

The specification describes several forms of trench gate MOS transistors and methods for making them. The structure further includes a pair of sidewall guards on opposing sidewalls to prevent inversion of the sidewalls when the trench gate is turned on.

Trench gate structures

A semiconductor read-only-memory (ROM) unit fabricated in large-scale-integrated form utilizing the formation of self-isolating bit-line surface regions of one conductivity type directly in a bulk region of the opposite conductivity type. Channel-stop regions of the same conductivity type as the bulk region are formed in the spaces between bit-line regions. Metallic word-lines overlying and orthogonal to the bit-line regions are formed, separated from the bit-line regions by an insulating layer. The memory cell comprises a single Schottky diode. Such a diode is made or not at each word-line/bit-line crossover location depending respectively on whether or not an aperture is formed in the insulating layer during fabrication to permit the word-line to contact a lightly doped portion of the bit-line. ROM units formed by this method are characterized by small area, high speed, low power dissipation and low cost.

Bipolar read-only-memory unit having self-isolating bit-lines

For identification purposes, a network is added to a multiply configurable microminiature array. During fabrication of the array, the connection pattern of the network is established to be uniquely representative of the particular circuit then being formed in the array. In response to interrogation signals applied to the array, the network provides a unique pattern of voltages representative of the particular circuit. During actual operation of the array, the identification network is in effect automatically disconnected therefrom.

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Allentown, PA, United States of America

Peter Theodore Panousis