Asml Netherlands B.v.

Peter Ten Berge

Everhardus Cornelis Mos

Michael Kubis

Franciscus Bernardus Maria Van Bilsen

Hoite Pieter Theodoor Tolsma

Christianus Gerardus Maria De Mol

Peter Hanzen Wardenier

Leonardus Henricus Marie Verstappen

Paul Jacques Van Wijnen

Gerald Dicker

Wouter Lodewijk Elings

Richard Johannes Franciscus Van Haren

Hubertus Johannes Gertrudus Simons

Reiner Maria Jungblut

Chung-Hsun Li

Erik Jensen

Henricus Wilhelmus Maria Van Buel

Hakki Ergün Cekli

Paul Cornelis Hubertus Aben

Nicole Schoumans

Christiaan Theodoor De Ruiter

Alexander Ypma

Boris Menchtchikov

Michael James Lercel

Chenxi Lin

Simon Hendrik Celine Van Gorp

Wolfgang Helmut Henke

David Frans Simon Deckers

Cyrus Emil Tabery

Simon Philip Spencer Hastings

Enno Van Den Brink

Dag Sonntag

Ruben Alvarez Sanchez

Keith Frank Best

Pierre-Yves Jerome Yvan Guittet

Shih-Chin Liu

Wei Duan

Johannes Catharinus Hubertus Mulkens

Cheng-Qun Gui

Franciscus Godefridus Casper Bijnen

Jochem Sebastiaan Wildenberg

Sarathi Roy

Daan Maurits Slotboom

Joseph Consolini

Erik Johannes Maria Wallerbos

Bernardo Kastrup

Marcus Theodoor Wilhelmus Van Der Heijden

Gerardus Johannes Joseph Keijsers

Pieter Gerardus Jacobus Smorenberg

Geoffrey Norman Phillipps

Budiman Sutedja

Khalid Elbattay

Joungchel Lee

Velislava Ignatova

Li Chung-Hsun

Markus Theodoor Wilhelmus Van Der Heijden

Steven Erik Steen

A method and associated apparatuses for optimizing a sampling scheme which defines sampling locations on a bonded substrate, having undergone a wafer to wafer bonding process. The method includes determining a sampling scheme for a metrology process and optimizing the sampling scheme with respect to a singularity defined by a large overlay error and/or grid deformation at a central location on the bonded substrate to obtain a modified sampling scheme.

Method for optimizing a sampling scheme and associated apparatuses

In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produced defined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is used to control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stacked to at least partially recompose the measurement results according to the sample plan.

Methods and apparatus for measuring a property of a substrate

A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.

Method for controlling a manufacturing process and associated apparatuses

A method and associated computer program for predicting an electrical characteristic of a substrate subject to a process. The method includes determining a sensitivity of the electrical characteristic to a process characteristic, based on analysis of electrical metrology data including electrical characteristic measurements from previously processed substrates and of process metrology data including measurements of at least one parameter related to the process characteristic measured from the previously processed substrates; obtaining process metrology data related to the substrate describing the at least one parameter; and predicting the electrical characteristic of the substrate based on the sensitivity and the process metrology data.

Method to predict yield of a device manufacturing process

A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool.

Inspection method and apparatus and lithographic processing cell

A method including evaluating, with respect to a parameter representing remaining uncertainty of a mathematical model fitting measured data, one or more mathematical models for fitting measured data and one or more measurement sampling schemes for measuring data, against measurement data across a substrate, and identifying one or more mathematical models and/or one or more measurement sampling schemes, for which the parameter crosses a threshold.

Method and apparatus for inspection and metrology

A method including: obtaining information regarding a patterning error in a patterning process involving a patterning device; determining a nonlinearity over a period of time introduced by modifying the patterning error by a modification apparatus according to the patterning error information; and determining a patterning error offset for use with the modification apparatus based on the determined nonlinearity.

Method and apparatus to reduce effects of nonlinear behavior

A method including: obtaining error information indicative of accuracy of positioning a pattern formed on a layer on a substrate relative to a target position, wherein the pattern has been formed by irradiating the layer with a radiation beam patterned by a patterning device; and producing modification information including a map of positional shifts across the patterning device so as to increase the accuracy of positioning the pattern formed using the patterning device modified according to the modification information, the modification information based on the error information, wherein the error information is independent of any other layer on the substrate.

Method and system for increasing accuracy of pattern positioning

A method including obtaining a measurement and/or simulation result of a pattern after being processed by an etch tool of a patterning system, determining a patterning error due to an etch loading effect based on the measurement and/or simulation result, and creating, by a computer system, modification information for modifying a patterning device and/or for adjusting a modification apparatus upstream in the patterning system from the etch tool based on the patterning error, wherein the patterning error is converted to a correctable error and/or reduced to a certain range, when the patterning device is modified according to the modification information and/or the modification apparatus is adjusted according to the modification information.

Method and apparatus to correct for patterning process error

A method, and associated system, for determining an optimized set of measurement locations for measurement of a parameter related to a structure applied to a substrate by a semiconductor manufacturing process. The method includes determining a first set of parameter values from a first set of measurements of first structures across a first plurality of locations, for example from target measurements and determining a second set of parameter values from a second set of measurements of second structures across a second plurality of locations, for example using an SEM or e-beam tool on product structures. A correlation is determined between the first set of parameter values and the second set of parameter values and used to determine the optimized set of measurement locations.

Method for determining an optimized set of measurement locations for measurement of a parameter of a lithographic process, metrology system and computer program products for implementing such methods

In the measurement of properties of a wafer substrate, such as Critical Dimension or overlay a sampling plan is produceddefined for measuring a property of a substrate, wherein the sampling plan comprises a plurality of sub-sampling plans. The sampling plan may be constrained to a predetermined fixed number of measurement points and is usedto control an inspection apparatus to perform a plurality of measurements of the property of a plurality of substrates using different sub-sampling plans for respective substrates, optionally, the results are stackedto at least partially recompose the measurement results according to the sample plan.

A method including: determining first error information based on a first measurement and/or simulation result pertaining to a first patterning device in a patterning system; determining second error information based on a second measurement and/or simulation result pertaining to a second patterning device in the patterning system; determining a difference between the first error information and the second error information; and creating modification information for the first patterning device and/or the second patterning device based on the difference between the first error information and the second error information, wherein the difference between the first error information and the second error information is reduced to within a certain range after the first patterning device and/or the second patterning device is modified according to the modification information.

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Eindhoven, Netherlands

Peter Ten Berge