International Business Machines Corporation

Peter T Fairchild

Joel C Leininger

Floyd R Bliss

A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.

Link register storage and restore system for use in an instruction

An interrupt system for an instruction pre-fetch microprocessor is provided. The interrupt system includes an instruction address register coupled to a storage address register for holding the next succeeding instruction address to the pre-fetched in a sequence of instructions. A storage address register is provided and is coupled to the instruction address register and is coupled to the storage address register for holding the storage address to be accessed. A first latch receives and stores an interrupt request from one of a plurality of peripheral devices. A second latch, enabling interrupts, is coupled to the storage unit and controlled by instructions from the microprocessor. An interrupt link register stores values of the instruction address register and page information together with arithmetic and logic unit status bits when an interrupt request has occurred from one of the plurality of peripheral devices and an interrupt cycle is executed. The system further includes an interrupt circuit coupled to the first and second latches for inhibiting updating of the instruction address register to a next succeeding instruction. Circuitry is coupled to the first and second latches for inhibiting the operation of the interrupt circuitry following a data storage cycle or a successful branch operation. Circuitry is also provided to cause the next instruction to be executed following an interrupt cycle to be fetched from a predefined word in storage.

Instruction pre-fetch microprocessor interrupt system

A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.

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Woodstock, GA, United States of America

Peter T Fairchild