Reservoir Labs, Inc.

Peter Szilagyi

Richard A Lethin

Jordi Ros-Giralt

David E Wohlford

Benoit J Meister

Nicolas T Vasilache

James Ezick

Allen K Leung

Cedric Bastoul

Systems, apparatus and methods for the implementation of high-speed network analyzers are provided. A set of high-level specifications is used to define the behavior of the network analyzer emitted by a compiler. An optimized inline workflow to process regular expressions is presented without sacrificing the semantic capabilities of the processing engine. An optimized packet dispatcher implements a subset of the functions implemented by the network analyzer, providing a fast and slow path workflow used to accelerate specific processing units. Such dispatcher facility can also be used as a cache of policies, wherein if a policy is found, then packet manipulations associated with the policy can be quickly performed. An optimized method of generating DFA specifications for network signatures is also presented. The method accepts several optimization criteria, such as min-max allocations or optimal allocations based on the probability of occurrence of each signature input bit.

System, apparatus and methods to implement high-speed network analyzers

Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that allow for parallel execution of tasks. The first custom computing apparatus optimizes the code for parallelism, locality of operations and contiguity of memory accesses on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

System, methods and apparatus for program optimization for multi-threaded processor architectures

In a multi-processor (e.g., multi-core) computer system, several processors can simultaneously access data without corruption thereof by: designating to each processor a portion of a hash table containing the data; by allowing each processor to access only those data elements belonging to the portion of the hash table designated to that processor; and by sending, via a network, other data elements to the processors that are designated the portions of the hash table to which the other data elements belong. The network avoids memory contention at each processor without requiring a memory-based lock. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Systems and methods for a fast interconnect table

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Medina, NY, United States of America

Peter Szilagyi